diff options
| author | Bob Wilson <bob.wilson@apple.com> | 2009-08-14 05:08:32 +0000 |
|---|---|---|
| committer | Bob Wilson <bob.wilson@apple.com> | 2009-08-14 05:08:32 +0000 |
| commit | 0ce371082565330672c276f76297f46b362d74b7 (patch) | |
| tree | e54bf3b9a0d45d35786649f61976d6a4af8e3965 /lib/Target/ARM/ARMISelLowering.cpp | |
| parent | 75caad4f1a0d9126fcdb1f7fbae1d343ff4c6f47 (diff) | |
During legalization, change Neon vdup_lane operations from shuffles to
target-specific VDUPLANE nodes. This allows the subreg handling for the
quad-register version to be done easily with Pats in the .td file, instead
of with custom code in ARMISelDAGToDAG.cpp.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78993 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM/ARMISelLowering.cpp')
| -rw-r--r-- | lib/Target/ARM/ARMISelLowering.cpp | 8 |
1 files changed, 7 insertions, 1 deletions
diff --git a/lib/Target/ARM/ARMISelLowering.cpp b/lib/Target/ARM/ARMISelLowering.cpp index a36fdbf247..3c40192ea5 100644 --- a/lib/Target/ARM/ARMISelLowering.cpp +++ b/lib/Target/ARM/ARMISelLowering.cpp @@ -477,7 +477,7 @@ const char *ARMTargetLowering::getTargetNodeName(unsigned Opcode) const { case ARMISD::VQRSHRNsu: return "ARMISD::VQRSHRNsu"; case ARMISD::VGETLANEu: return "ARMISD::VGETLANEu"; case ARMISD::VGETLANEs: return "ARMISD::VGETLANEs"; - case ARMISD::VDUPLANEQ: return "ARMISD::VDUPLANEQ"; + case ARMISD::VDUPLANE: return "ARMISD::VDUPLANE"; case ARMISD::VLD2D: return "ARMISD::VLD2D"; case ARMISD::VLD3D: return "ARMISD::VLD3D"; case ARMISD::VLD4D: return "ARMISD::VLD4D"; @@ -2447,6 +2447,12 @@ static SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) { // of inconsistencies between legalization and selection. // FIXME: floating-point vectors should be canonicalized to integer vectors // of the same time so that they get CSEd properly. + if (SVN->isSplat()) { + int Lane = SVN->getSplatIndex(); + if (Lane != 0) + return DAG.getNode(ARMISD::VDUPLANE, dl, VT, SVN->getOperand(0), + DAG.getConstant(Lane, MVT::i32)); + } if (isVREVMask(SVN, 64)) return DAG.getNode(ARMISD::VREV64, dl, VT, SVN->getOperand(0)); if (isVREVMask(SVN, 32)) |