diff options
| author | Andrew Trick <atrick@apple.com> | 2011-08-25 17:50:53 +0000 |
|---|---|---|
| committer | Andrew Trick <atrick@apple.com> | 2011-08-25 17:50:53 +0000 |
| commit | b9ca5124f8a5d593f57cbd0566867578a51d7055 (patch) | |
| tree | 706e508b235bcd0d26078ab23d34c789eff013df /lib/Target/ARM/ARMFrameLowering.cpp | |
| parent | 51972da57615d7d31372dd1fef120333ef2d799c (diff) | |
ARM fix for missing implicit operands on ldmia_ret.
rdar://10005094: miscompile of 176.gcc
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138568 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM/ARMFrameLowering.cpp')
| -rw-r--r-- | lib/Target/ARM/ARMFrameLowering.cpp | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/lib/Target/ARM/ARMFrameLowering.cpp b/lib/Target/ARM/ARMFrameLowering.cpp index 85c284f02a..8fe3f39da8 100644 --- a/lib/Target/ARM/ARMFrameLowering.cpp +++ b/lib/Target/ARM/ARMFrameLowering.cpp @@ -646,8 +646,10 @@ void ARMFrameLowering::emitPopInst(MachineBasicBlock &MBB, .addReg(ARM::SP)); for (unsigned i = 0, e = Regs.size(); i < e; ++i) MIB.addReg(Regs[i], getDefRegState(true)); - if (DeleteRet) + if (DeleteRet) { + MIB->copyImplicitOps(&*MI); MI->eraseFromParent(); + } MI = MIB; } else if (Regs.size() == 1) { // If we adjusted the reg to PC from LR above, switch it back here. We |