diff options
| author | Jim Grosbach <grosbach@apple.com> | 2010-10-26 22:37:02 +0000 |
|---|---|---|
| committer | Jim Grosbach <grosbach@apple.com> | 2010-10-26 22:37:02 +0000 |
| commit | 3e5561247202bae994dd259a2d8dc4eff8f799f3 (patch) | |
| tree | 4a3d53fc109ee222ad3a4dae98373aca68dcff1f /lib/Target/ARM/ARMFastISel.cpp | |
| parent | 3a0e0715a5691e26ca70bc853d6d3d116e5949b8 (diff) | |
First part of refactoring ARM addrmode2 (load/store) instructions to be more
explicit about the operands. Split out the different variants into separate
instructions. This gives us the ability to, among other things, assign
different scheduling itineraries to the variants. rdar://8477752.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117409 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM/ARMFastISel.cpp')
| -rw-r--r-- | lib/Target/ARM/ARMFastISel.cpp | 15 |
1 files changed, 5 insertions, 10 deletions
diff --git a/lib/Target/ARM/ARMFastISel.cpp b/lib/Target/ARM/ARMFastISel.cpp index bbaa308ee8..7cf7ec0355 100644 --- a/lib/Target/ARM/ARMFastISel.cpp +++ b/lib/Target/ARM/ARMFastISel.cpp @@ -449,7 +449,7 @@ unsigned ARMFastISel::ARMMaterializeInt(const Constant *C, EVT VT) { AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(ARM::LDRcp), DestReg) .addConstantPoolIndex(Idx) - .addReg(0).addImm(0)); + .addImm(0)); return DestReg; } @@ -750,7 +750,7 @@ bool ARMFastISel::ARMEmitLoad(EVT VT, unsigned &ResultReg, RC = ARM::GPRRegisterClass; break; case MVT::i32: - Opc = isThumb ? ARM::t2LDRi12 : ARM::LDR; + Opc = isThumb ? ARM::t2LDRi12 : ARM::LDRi12; RC = ARM::GPRRegisterClass; break; case MVT::f32: @@ -776,14 +776,9 @@ bool ARMFastISel::ARMEmitLoad(EVT VT, unsigned &ResultReg, // The thumb and floating point instructions both take 2 operands, ARM takes // another register. - if (isFloat || isThumb) - AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, - TII.get(Opc), ResultReg) - .addReg(Base).addImm(Offset)); - else - AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, - TII.get(Opc), ResultReg) - .addReg(Base).addReg(0).addImm(Offset)); + AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, + TII.get(Opc), ResultReg) + .addReg(Base).addImm(Offset)); return true; } |