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authorJakob Stoklund Olesen <stoklund@2pi.dk>2010-04-05 03:10:20 +0000
committerJakob Stoklund Olesen <stoklund@2pi.dk>2010-04-05 03:10:20 +0000
commitfddb7667ca4d8fe83f96b388295849281ddaa5b4 (patch)
treefdfe17e6a728d6560f0217760d6e3dd80ca924ed /lib/Target/ARM/ARM.td
parentba79d72eab446e64d360e8263d77732b5e13d556 (diff)
Replace TSFlagsFields and TSFlagsShifts with a simpler TSFlags field.
When a target instruction wants to set target-specific flags, it should simply set bits in the TSFlags bit vector defined in the Instruction TableGen class. This works well because TableGen resolves member references late: class I : Instruction { AddrMode AM = AddrModeNone; let TSFlags{3-0} = AM.Value; } let AM = AddrMode4 in def ADD : I; TSFlags gets the expected bits from AddrMode4 in this example. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100384 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM/ARM.td')
-rw-r--r--lib/Target/ARM/ARM.td18
1 files changed, 1 insertions, 17 deletions
diff --git a/lib/Target/ARM/ARM.td b/lib/Target/ARM/ARM.td
index 6486a608e4..8d9c62253c 100644
--- a/lib/Target/ARM/ARM.td
+++ b/lib/Target/ARM/ARM.td
@@ -140,23 +140,7 @@ include "ARMCallingConv.td"
include "ARMInstrInfo.td"
-def ARMInstrInfo : InstrInfo {
- // Define how we want to layout our target-specific information field.
- let TSFlagsFields = ["AddrModeBits",
- "SizeFlag",
- "IndexModeBits",
- "Form",
- "isUnaryDataProc",
- "canXformTo16Bit",
- "Dom"];
- let TSFlagsShifts = [0,
- 4,
- 7,
- 9,
- 15,
- 16,
- 17];
-}
+def ARMInstrInfo : InstrInfo;
//===----------------------------------------------------------------------===//
// Declare the target which we are implementing