diff options
| author | Tim Northover <Tim.Northover@arm.com> | 2013-02-05 13:24:56 +0000 |
|---|---|---|
| committer | Tim Northover <Tim.Northover@arm.com> | 2013-02-05 13:24:56 +0000 |
| commit | dfe076af9879eb68a7b8331f9c02eecf563d85be (patch) | |
| tree | e1c1993543cc51da36b9cfc99ca0e7104a28ef33 /lib/Target/AArch64/Utils/AArch64BaseInfo.cpp | |
| parent | 19254c49a8752fe8c6fa648a6eb29f20a1f62c8b (diff) | |
Fix formatting in AArch64 backend.
This should fix three purely whitespace issues:
+ 80 column violations.
+ Tab characters.
+ TableGen brace placement.
No functional changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174370 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/AArch64/Utils/AArch64BaseInfo.cpp')
| -rw-r--r-- | lib/Target/AArch64/Utils/AArch64BaseInfo.cpp | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/lib/Target/AArch64/Utils/AArch64BaseInfo.cpp b/lib/Target/AArch64/Utils/AArch64BaseInfo.cpp index cf9a638b5d..5f09074bcf 100644 --- a/lib/Target/AArch64/Utils/AArch64BaseInfo.cpp +++ b/lib/Target/AArch64/Utils/AArch64BaseInfo.cpp @@ -725,7 +725,8 @@ bool A64Imms::isLogicalImm(unsigned RegWidth, uint64_t Imm, uint32_t &Bits) { } -bool A64Imms::isLogicalImmBits(unsigned RegWidth, uint32_t Bits, uint64_t &Imm) { +bool A64Imms::isLogicalImmBits(unsigned RegWidth, uint32_t Bits, + uint64_t &Imm) { uint32_t N = Bits >> 12; uint32_t ImmR = (Bits >> 6) & 0x3f; uint32_t ImmS = Bits & 0x3f; |