Move some methods out of MachineInstr into MachineOperand

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28102 91177308-0d34-0410-b5e6-96231b3b80d8

6 files changed, 16 insertions, 35 deletions

diff --git a/lib/CodeGen/LiveIntervalAnalysis.cpp b/lib/CodeGen/LiveIntervalAnalysis.cpp
index 8c28c97b0a..17144f5582 100644
--- a/lib/CodeGen/LiveIntervalAnalysis.cpp
+++ b/lib/CodeGen/LiveIntervalAnalysis.cpp
@@ -187,7 +187,7 @@ bool LiveIntervals::runOnMachineFunction(MachineFunction &fn) {
               MRegisterInfo::isVirtualRegister(mop.getReg())) {
             // replace register with representative register
             unsigned reg = rep(mop.getReg());
-            mii->SetMachineOperandReg(i, reg);
+            mii->getOperand(i).setReg(reg);
 
             LiveInterval &RegInt = getInterval(reg);
             RegInt.weight +=
@@ -263,7 +263,7 @@ addIntervalsForSpills(const LiveInterval &li, VirtRegMap &vrm, int slot) {
           if (NewRegLiveIn && mop.isUse()) {
             // We already emitted a reload of this value, reuse it for
             // subsequent operands.
-            MI->SetMachineOperandReg(i, NewRegLiveIn);
+            MI->getOperand(i).setReg(NewRegLiveIn);
             DEBUG(std::cerr << "\t\t\t\treused reload into reg" << NewRegLiveIn
                             << " for operand #" << i << '\n');
           } else if (MachineInstr* fmi = mri_->foldMemoryOperand(MI, i, slot)) {
@@ -300,7 +300,7 @@ addIntervalsForSpills(const LiveInterval &li, VirtRegMap &vrm, int slot) {
 
             // create a new register for this spill
             NewRegLiveIn = mf_->getSSARegMap()->createVirtualRegister(rc);
-            MI->SetMachineOperandReg(i, NewRegLiveIn);
+            MI->getOperand(i).setReg(NewRegLiveIn);
             vrm.grow();
             vrm.assignVirt2StackSlot(NewRegLiveIn, slot);
             LiveInterval& nI = getOrCreateInterval(NewRegLiveIn);
diff --git a/lib/CodeGen/MachineInstr.cpp b/lib/CodeGen/MachineInstr.cpp
index 90cec5a0a0..b1fb52a13a 100644
--- a/lib/CodeGen/MachineInstr.cpp
+++ b/lib/CodeGen/MachineInstr.cpp
@@ -107,25 +107,6 @@ bool MachineInstr::OperandsComplete() const {
   return false;
 }
 
-void
-MachineInstr::SetMachineOperandConst(unsigned i,
-                                     MachineOperand::MachineOperandType opTy,
-                                     int intValue) {
-  assert(i < getNumOperands());
-  operands[i].opType = opTy;
-  operands[i].contents.immedVal = intValue;
-  operands[i].extra.regNum = -1;
-  operands[i].flags = 0;
-}
-
-void MachineInstr::SetMachineOperandReg(unsigned i, int regNum) {
-  assert(i < getNumOperands());
-
-  operands[i].opType = MachineOperand::MO_VirtualRegister;
-  operands[i].contents.GV = NULL;
-  operands[i].extra.regNum = regNum;
-}
-
 void MachineInstr::dump() const {
   std::cerr << "  " << *this;
 }
diff --git a/lib/CodeGen/RegAllocLocal.cpp b/lib/CodeGen/RegAllocLocal.cpp
index f84f7e82ef..e3921e4ed3 100644
--- a/lib/CodeGen/RegAllocLocal.cpp
+++ b/lib/CodeGen/RegAllocLocal.cpp
@@ -443,7 +443,7 @@ MachineInstr *RA::reloadVirtReg(MachineBasicBlock &MBB, MachineInstr *MI,
   // and return.
   if (unsigned PR = getVirt2PhysRegMapSlot(VirtReg)) {
     MarkPhysRegRecentlyUsed(PR);          // Already have this value available!
-    MI->SetMachineOperandReg(OpNum, PR);  // Assign the input register
+    MI->getOperand(OpNum).setReg(PR);  // Assign the input register
     return MI;
   }
 
@@ -481,7 +481,7 @@ MachineInstr *RA::reloadVirtReg(MachineBasicBlock &MBB, MachineInstr *MI,
   ++NumLoads;    // Update statistics
 
   PhysRegsEverUsed[PhysReg] = true;
-  MI->SetMachineOperandReg(OpNum, PhysReg);  // Assign the input register
+  MI->getOperand(OpNum).setReg(PhysReg);  // Assign the input register
   return MI;
 }
 
@@ -599,7 +599,7 @@ void RA::AllocateBasicBlock(MachineBasicBlock &MBB) {
           DestPhysReg = getReg(MBB, MI, DestVirtReg);
         PhysRegsEverUsed[DestPhysReg] = true;
         markVirtRegModified(DestVirtReg);
-        MI->SetMachineOperandReg(i, DestPhysReg);  // Assign the output register
+        MI->getOperand(i).setReg(DestPhysReg);  // Assign the output register
       }
     }
 
diff --git a/lib/CodeGen/RegAllocSimple.cpp b/lib/CodeGen/RegAllocSimple.cpp
index f6a9a112df..4e6e1d2705 100644
--- a/lib/CodeGen/RegAllocSimple.cpp
+++ b/lib/CodeGen/RegAllocSimple.cpp
@@ -211,7 +211,7 @@ void RegAllocSimple::AllocateBasicBlock(MachineBasicBlock &MBB) {
             Virt2PhysRegMap[virtualReg] = physReg;
           }
         }
-        MI->SetMachineOperandReg(i, physReg);
+        MI->getOperand(i).setReg(physReg);
         DEBUG(std::cerr << "virt: " << virtualReg <<
               ", phys: " << op.getReg() << "\n");
       }
diff --git a/lib/CodeGen/TwoAddressInstructionPass.cpp b/lib/CodeGen/TwoAddressInstructionPass.cpp
index 48581eebc1..4bd20479ff 100644
--- a/lib/CodeGen/TwoAddressInstructionPass.cpp
+++ b/lib/CodeGen/TwoAddressInstructionPass.cpp
@@ -200,7 +200,7 @@ bool TwoAddressInstructionPass::runOnMachineFunction(MachineFunction &MF) {
         for (unsigned i = 1, e = mi->getNumOperands(); i != e; ++i) {
           if (mi->getOperand(i).isRegister() &&
               mi->getOperand(i).getReg() == regB)
-            mi->SetMachineOperandReg(i, regA);
+            mi->getOperand(i).setReg(regA);
         }
       }
 
diff --git a/lib/CodeGen/VirtRegMap.cpp b/lib/CodeGen/VirtRegMap.cpp
index 912359d137..533a53b8e8 100644
--- a/lib/CodeGen/VirtRegMap.cpp
+++ b/lib/CodeGen/VirtRegMap.cpp
@@ -182,7 +182,7 @@ bool SimpleSpiller::runOnMachineFunction(MachineFunction &MF, VirtRegMap &VRM) {
               }
             }
             PhysRegsUsed[PhysReg] = true;
-            MI.SetMachineOperandReg(i, PhysReg);
+            MI.getOperand(i).setReg(PhysReg);
           } else {
             PhysRegsUsed[MO.getReg()] = true;
           }
@@ -458,7 +458,7 @@ namespace {
             // Any stores to this stack slot are not dead anymore.
             MaybeDeadStores.erase(NewOp.StackSlot);
             
-            MI->SetMachineOperandReg(NewOp.Operand, NewPhysReg);
+            MI->getOperand(NewOp.Operand).setReg(NewPhysReg);
             
             Spills.addAvailable(NewOp.StackSlot, NewPhysReg);
             ++NumLoads;
@@ -536,7 +536,7 @@ void LocalSpiller::RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM) {
         // This virtual register was assigned a physreg!
         unsigned Phys = VRM.getPhys(VirtReg);
         PhysRegsUsed[Phys] = true;
-        MI.SetMachineOperandReg(i, Phys);
+        MI.getOperand(i).setReg(Phys);
         continue;
       }
       
@@ -567,7 +567,7 @@ void LocalSpiller::RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM) {
                           << MRI->getName(PhysReg) << " for vreg"
                           << VirtReg <<" instead of reloading into physreg "
                           << MRI->getName(VRM.getPhys(VirtReg)) << "\n");
-          MI.SetMachineOperandReg(i, PhysReg);
+          MI.getOperand(i).setReg(PhysReg);
 
           // The only technical detail we have is that we don't know that
           // PhysReg won't be clobbered by a reloaded stack slot that occurs
@@ -618,7 +618,7 @@ void LocalSpiller::RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM) {
                           << MRI->getName(PhysReg) << " for vreg"
                           << VirtReg
                           << " instead of reloading into same physreg.\n");
-          MI.SetMachineOperandReg(i, PhysReg);
+          MI.getOperand(i).setReg(PhysReg);
           ++NumReused;
           continue;
         }
@@ -633,7 +633,7 @@ void LocalSpiller::RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM) {
         Spills.ClobberPhysReg(DesignatedReg);
         
         Spills.addAvailable(StackSlot, DesignatedReg);
-        MI.SetMachineOperandReg(i, DesignatedReg);
+        MI.getOperand(i).setReg(DesignatedReg);
         DEBUG(std::cerr << '\t' << *prior(MII));
         ++NumReused;
         continue;
@@ -662,7 +662,7 @@ void LocalSpiller::RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM) {
       MaybeDeadStores.erase(StackSlot);
       Spills.addAvailable(StackSlot, PhysReg);
       ++NumLoads;
-      MI.SetMachineOperandReg(i, PhysReg);
+      MI.getOperand(i).setReg(PhysReg);
       DEBUG(std::cerr << '\t' << *prior(MII));
     }
 
@@ -817,7 +817,7 @@ void LocalSpiller::RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM) {
         PhysRegsUsed[PhysReg] = true;
         MRI->storeRegToStackSlot(MBB, next(MII), PhysReg, StackSlot, RC);
         DEBUG(std::cerr << "Store:\t" << *next(MII));
-        MI.SetMachineOperandReg(i, PhysReg);
+        MI.getOperand(i).setReg(PhysReg);
 
         // Check to see if this is a noop copy.  If so, eliminate the
         // instruction before considering the dest reg to be changed.