* Fix a GlobalAddress lowering bug.

* Teach DAG combiner about X86ISD::SETCC by adding a TargetLowering hook.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24921 91177308-0d34-0410-b5e6-96231b3b80d8

2 files changed, 9 insertions, 1 deletions

diff --git a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index ddd8549a09..87c6cf0f90 100644
--- a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -455,7 +455,10 @@ static bool MaskedValueIsZero(const SDOperand &Op, uint64_t Mask,
     // Bit counting instructions can not set the high bits of the result
     // register.  The max number of bits sets depends on the input.
     return (Mask & (MVT::getSizeInBits(Op.getValueType())*2-1)) == 0;
-  default: break;
+  default:
+    if (Op.getOpcode() >= ISD::BUILTIN_OP_END)
+      return TLI.isMaskedValueZeroForTargetNode(Op, Mask);
+    break;
   }
   return false;
 }
diff --git a/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/lib/CodeGen/SelectionDAG/TargetLowering.cpp
index 8e9524ef1e..e46826e2fa 100644
--- a/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+++ b/lib/CodeGen/SelectionDAG/TargetLowering.cpp
@@ -125,3 +125,8 @@ void TargetLowering::computeRegisterProperties() {
 const char *TargetLowering::getTargetNodeName(unsigned Opcode) const {
   return NULL;
 }
+
+bool isMaskedValueZeroForTargetNode(const SDOperand &Op,
+                                    uint64_t Mask) const {
+  return false;
+}