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authorJakob Stoklund Olesen <stoklund@2pi.dk>2012-12-03 23:23:50 +0000
committerJakob Stoklund Olesen <stoklund@2pi.dk>2012-12-03 23:23:50 +0000
commitfc6374439edf2f74da4026f4cea8e341d092be5c (patch)
treebb000dd3e82cff7fae77dcf0f9d9930922e4e1f4 /lib/CodeGen/VirtRegMap.cpp
parentade047463fd6e0fbb447145eb06015b8e7836482 (diff)
Add VirtRegMap::hasKnownPreference().
Virtual registers with a known preferred register are prioritized by RAGreedy. This function makes the condition explicit without depending on getRegAllocPref(). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169179 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/CodeGen/VirtRegMap.cpp')
-rw-r--r--lib/CodeGen/VirtRegMap.cpp9
1 files changed, 9 insertions, 0 deletions
diff --git a/lib/CodeGen/VirtRegMap.cpp b/lib/CodeGen/VirtRegMap.cpp
index cf674575ba..dcfad66414 100644
--- a/lib/CodeGen/VirtRegMap.cpp
+++ b/lib/CodeGen/VirtRegMap.cpp
@@ -88,6 +88,15 @@ unsigned VirtRegMap::getRegAllocPref(unsigned virtReg) {
return TRI->ResolveRegAllocHint(Hint.first, physReg, *MF);
}
+bool VirtRegMap::hasKnownPreference(unsigned VirtReg) {
+ std::pair<unsigned, unsigned> Hint = MRI->getRegAllocationHint(VirtReg);
+ if (TargetRegisterInfo::isPhysicalRegister(Hint.second))
+ return true;
+ if (TargetRegisterInfo::isVirtualRegister(Hint.second))
+ return hasPhys(Hint.second);
+ return false;
+}
+
int VirtRegMap::assignVirt2StackSlot(unsigned virtReg) {
assert(TargetRegisterInfo::isVirtualRegister(virtReg));
assert(Virt2StackSlotMap[virtReg] == NO_STACK_SLOT &&