diff options
| author | Misha Brukman <brukman+llvm@gmail.com> | 2005-04-21 22:36:52 +0000 |
|---|---|---|
| committer | Misha Brukman <brukman+llvm@gmail.com> | 2005-04-21 22:36:52 +0000 |
| commit | edf128a7fa90f2b0b7ee24741a04a7ae1ecd6f7e (patch) | |
| tree | 3a2bd1b8b76e3380197d77448d1eebddf6259ce0 /lib/CodeGen/TwoAddressInstructionPass.cpp | |
| parent | 23c6d2cb795ba0e7f132648ced6531a8abaa0d96 (diff) | |
Remove trailing whitespace
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21420 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/CodeGen/TwoAddressInstructionPass.cpp')
| -rw-r--r-- | lib/CodeGen/TwoAddressInstructionPass.cpp | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/lib/CodeGen/TwoAddressInstructionPass.cpp b/lib/CodeGen/TwoAddressInstructionPass.cpp index df632100de..2e6d8260e3 100644 --- a/lib/CodeGen/TwoAddressInstructionPass.cpp +++ b/lib/CodeGen/TwoAddressInstructionPass.cpp @@ -57,7 +57,7 @@ namespace { bool runOnMachineFunction(MachineFunction&); }; - RegisterPass<TwoAddressInstructionPass> + RegisterPass<TwoAddressInstructionPass> X("twoaddressinstruction", "Two-Address instruction pass"); }; @@ -152,7 +152,7 @@ bool TwoAddressInstructionPass::runOnMachineFunction(MachineFunction &MF) { mbbi->insert(mi, NewMI); // Insert the new inst mbbi->erase(mi); // Nuke the old inst. mi = NewMI; - } + } ++NumCommuted; regB = regC; @@ -161,7 +161,7 @@ bool TwoAddressInstructionPass::runOnMachineFunction(MachineFunction &MF) { } } // If this instruction is potentially convertible to a true - // three-address instruction, + // three-address instruction, if (TID.Flags & M_CONVERTIBLE_TO_3_ADDR) if (MachineInstr *New = TII.convertToThreeAddress(mi)) { DEBUG(std::cerr << "2addr: CONVERTING 2-ADDR: " << *mi); @@ -197,7 +197,7 @@ bool TwoAddressInstructionPass::runOnMachineFunction(MachineFunction &MF) { // replace all occurences of regB with regA for (unsigned i = 1, e = mi->getNumOperands(); i != e; ++i) { - if (mi->getOperand(i).isRegister() && + if (mi->getOperand(i).isRegister() && mi->getOperand(i).getReg() == regB) mi->SetMachineOperandReg(i, regA); } |