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authorAlexander Kornienko <alexfh@google.com>2013-03-26 02:28:59 +0000
committerAlexander Kornienko <alexfh@google.com>2013-03-26 02:28:59 +0000
commitd934545ae6a00aa8a8179a93d11cbd93a5240849 (patch)
treeab44db08aa63a8f94a3e09d6491c4156c624af96 /lib/CodeGen/TargetSchedule.cpp
parent868d4470cdfa9472353ea2a49a6c456ddae9c95b (diff)
parentc204410d6bc435e7cb8ea768759a54135e8e92b5 (diff)
Updating branches/google/testing to r177703testing
git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/google/testing@177985 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/CodeGen/TargetSchedule.cpp')
-rw-r--r--lib/CodeGen/TargetSchedule.cpp5
1 files changed, 4 insertions, 1 deletions
diff --git a/lib/CodeGen/TargetSchedule.cpp b/lib/CodeGen/TargetSchedule.cpp
index f31f67d58c..783bfa1c1a 100644
--- a/lib/CodeGen/TargetSchedule.cpp
+++ b/lib/CodeGen/TargetSchedule.cpp
@@ -240,7 +240,10 @@ unsigned TargetSchedModel::computeOperandLatency(
report_fatal_error(ss.str());
}
#endif
- return DefMI->isTransient() ? 0 : 1;
+ // FIXME: Automatically giving all implicit defs defaultDefLatency is
+ // undesirable. We should only do it for defs that are known to the MC
+ // desc like flags. Truly implicit defs should get 1 cycle latency.
+ return DefMI->isTransient() ? 0 : TII->defaultDefLatency(&SchedModel, DefMI);
}
unsigned TargetSchedModel::computeInstrLatency(const MachineInstr *MI) const {