Extensive additions for supporting instruction scheduling.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@398 91177308-0d34-0410-b5e6-96231b3b80d8

1 files changed, 73 insertions, 2 deletions

diff --git a/lib/CodeGen/TargetMachine/Sparc/Sparc.cpp b/lib/CodeGen/TargetMachine/Sparc/Sparc.cpp
index 4707b373b9..f66d10e749 100644
--- a/lib/CodeGen/TargetMachine/Sparc/Sparc.cpp
+++ b/lib/CodeGen/TargetMachine/Sparc/Sparc.cpp
@@ -14,6 +14,70 @@
 //************************ Class Implementations **************************/
 
 
+//---------------------------------------------------------------------------
+// class UltraSparcInstrInfo 
+// 
+// Purpose:
+//   Information about individual instructions.
+//   Most information is stored in the SparcMachineInstrDesc array above.
+//   Other information is computed on demand, and most such functions
+//   default to member functions in base class MachineInstrInfo. 
+//---------------------------------------------------------------------------
+
+/*ctor*/
+UltraSparcInstrInfo::UltraSparcInstrInfo()
+  : MachineInstrInfo(SparcMachineInstrDesc,
+		     /*descSize = */ NUM_TOTAL_OPCODES,
+		     /*numRealOpCodes = */ NUM_REAL_OPCODES)
+{
+}
+
+
+//---------------------------------------------------------------------------
+// class UltraSparcSchedInfo 
+// 
+// Purpose:
+//   Scheduling information for the UltraSPARC.
+//   Primarily just initializes machine-dependent parameters in
+//   class MachineSchedInfo.
+//---------------------------------------------------------------------------
+
+/*ctor*/
+UltraSparcSchedInfo::UltraSparcSchedInfo(const MachineInstrInfo* mii)
+  : MachineSchedInfo((unsigned int) SPARC_NUM_SCHED_CLASSES,
+		     mii,
+		     SparcRUsageDesc,
+		     SparcInstrUsageDeltas,
+		     SparcInstrIssueDeltas,
+		     sizeof(SparcInstrUsageDeltas)/sizeof(InstrRUsageDelta),
+		     sizeof(SparcInstrIssueDeltas)/sizeof(InstrIssueDelta))
+{
+  maxNumIssueTotal = 4;
+  longestIssueConflict = 0;		// computed from issuesGaps[]
+  
+  branchMispredictPenalty = 4;		// 4 for SPARC IIi
+  branchTargetUnknownPenalty = 2;	// 2 for SPARC IIi
+  l1DCacheMissPenalty = 8;		// 7 or 9 for SPARC IIi
+  l1ICacheMissPenalty = 8;		// ? for SPARC IIi
+  
+  inOrderLoads = true;			// true for SPARC IIi
+  inOrderIssue = true;			// true for SPARC IIi
+  inOrderExec  = false;			// false for most architectures
+  inOrderRetire= true;			// true for most architectures
+  
+  // must be called after above parameters are initialized.
+  this->initializeResources();
+}
+
+void
+UltraSparcSchedInfo::initializeResources()
+{
+  // Compute MachineSchedInfo::instrRUsages and MachineSchedInfo::issueGaps
+  MachineSchedInfo::initializeResources();
+  
+  // Machine-dependent fixups go here.  None for now.
+}
+
 
 //---------------------------------------------------------------------------
 // class UltraSparcMachine 
@@ -27,14 +91,21 @@
 //---------------------------------------------------------------------------
 
 UltraSparc::UltraSparc()
-  : TargetMachine("UltraSparc-Native", new UltraSparcInstrInfo()) {
+  : TargetMachine("UltraSparc-Native")
+{
+  machineInstrInfo = new UltraSparcInstrInfo;
+  machineSchedInfo = new UltraSparcSchedInfo(machineInstrInfo); 
+  
   optSizeForSubWordData = 4;
   minMemOpWordSize = 8; 
   maxAtomicMemOpWordSize = 8;
   zeroRegNum = 0;			// %g0 always gives 0 on Sparc
 }
 
-UltraSparc::~UltraSparc() {
+UltraSparc::~UltraSparc()
+{
+  delete (UltraSparcInstrInfo*) machineInstrInfo;
+  delete (UltraSparcSchedInfo*) machineSchedInfo;
 }
 
 //**************************************************************************/