Remove trailing whitespace

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21420 91177308-0d34-0410-b5e6-96231b3b80d8

4 files changed, 105 insertions, 105 deletions

diff --git a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
index 3df6244757..12938e6e57 100644
--- a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
+++ b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
@@ -1,10 +1,10 @@
 //===-- LegalizeDAG.cpp - Implement SelectionDAG::Legalize ----------------===//
-// 
+//
 //                     The LLVM Compiler Infrastructure
 //
 // This file was developed by the LLVM research group and is distributed under
 // the University of Illinois Open Source License. See LICENSE.TXT for details.
-// 
+//
 //===----------------------------------------------------------------------===//
 //
 // This file implements the SelectionDAG::Legalize method.
@@ -285,7 +285,7 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
         VT = MVT::f32;
         Extend = true;
       }
-      
+
       SDOperand CPIdx = DAG.getConstantPool(CP->getConstantPoolIndex(LLVMC),
                                             TLI.getPointerTy());
       if (Extend) {
@@ -433,7 +433,7 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
       Result = DAG.getLoad(Node->getValueType(0), Tmp1, Tmp2);
     else
       Result = SDOperand(Node, 0);
-    
+
     // Since loads produce two values, make sure to remember that we legalized
     // both of them.
     AddLegalizedOperand(SDOperand(Node, 0), Result);
@@ -458,7 +458,7 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
       AddLegalizedOperand(SDOperand(Node, 0), Result);
       AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
       return Result.getValue(Op.ResNo);
-      
+
     case TargetLowering::Legal:
       if (Tmp1 != Node->getOperand(0) ||
           Tmp2 != Node->getOperand(1))
@@ -504,7 +504,7 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
 
   case ISD::CopyToReg:
     Tmp1 = LegalizeOp(Node->getOperand(0));  // Legalize the chain.
-    
+
     switch (getTypeAction(Node->getOperand(1).getValueType())) {
     case Legal:
       // Legalize the incoming value (must be legal).
@@ -518,7 +518,7 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
       break;
     case Expand:
       SDOperand Lo, Hi;
-      ExpandOp(Node->getOperand(1), Lo, Hi);      
+      ExpandOp(Node->getOperand(1), Lo, Hi);
       unsigned Reg = cast<RegSDNode>(Node)->getReg();
       Lo = DAG.getCopyToReg(Tmp1, Lo, Reg);
       Hi = DAG.getCopyToReg(Tmp1, Hi, Reg+1);
@@ -544,7 +544,7 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
         SDOperand Lo, Hi;
         ExpandOp(Node->getOperand(1), Lo, Hi);
         Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Hi);
-        break;                             
+        break;
       }
       case Promote:
         Tmp2 = PromoteOp(Node->getOperand(1));
@@ -569,7 +569,7 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
           ExpandOp(Node->getOperand(i), Lo, Hi);
           NewValues.push_back(Lo);
           NewValues.push_back(Hi);
-          break;                             
+          break;
         }
         case Promote:
           assert(0 && "Can't promote multiple return value yet!");
@@ -753,7 +753,7 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
       Result = DAG.getSetCC(cast<SetCCSDNode>(Node)->getCondition(),
                             Node->getValueType(0), Tmp1, Tmp2);
       break;
-    case Expand: 
+    case Expand:
       SDOperand LHSLo, LHSHi, RHSLo, RHSHi;
       ExpandOp(Node->getOperand(0), LHSLo, LHSHi);
       ExpandOp(Node->getOperand(1), RHSLo, RHSHi);
@@ -765,15 +765,15 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
             if (RHSCST->isAllOnesValue()) {
               // Comparison to -1.
               Tmp1 = DAG.getNode(ISD::AND, LHSLo.getValueType(), LHSLo, LHSHi);
-              Result = DAG.getSetCC(cast<SetCCSDNode>(Node)->getCondition(), 
+              Result = DAG.getSetCC(cast<SetCCSDNode>(Node)->getCondition(),
                                     Node->getValueType(0), Tmp1, RHSLo);
-              break;                                    
+              break;
             }
 
         Tmp1 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSLo, RHSLo);
         Tmp2 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSHi, RHSHi);
         Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp2);
-        Result = DAG.getSetCC(cast<SetCCSDNode>(Node)->getCondition(), 
+        Result = DAG.getSetCC(cast<SetCCSDNode>(Node)->getCondition(),
                               Node->getValueType(0), Tmp1,
                               DAG.getConstant(0, Tmp1.getValueType()));
         break;
@@ -781,7 +781,7 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
         // If this is a comparison of the sign bit, just look at the top part.
         // X > -1,  x < 0
         if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Node->getOperand(1)))
-          if ((cast<SetCCSDNode>(Node)->getCondition() == ISD::SETLT && 
+          if ((cast<SetCCSDNode>(Node)->getCondition() == ISD::SETLT &&
                CST->getValue() == 0) ||              // X < 0
               (cast<SetCCSDNode>(Node)->getCondition() == ISD::SETGT &&
                (CST->isAllOnesValue())))             // X > -1
@@ -801,7 +801,7 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
         case ISD::SETGE:
         case ISD::SETUGE: LowCC = ISD::SETUGE; break;
         }
-        
+
         // Tmp1 = lo(op1) < lo(op2)   // Always unsigned comparison
         // Tmp2 = hi(op1) < hi(op2)   // Signedness depends on operands
         // dest = hi(op1) == hi(op2) ? Tmp1 : Tmp2;
@@ -836,7 +836,7 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
         break;
       }
     } else {
-      Tmp3 = LegalizeOp(Node->getOperand(2));    // memcpy/move = pointer, 
+      Tmp3 = LegalizeOp(Node->getOperand(2));    // memcpy/move = pointer,
     }
 
     SDOperand Tmp4;
@@ -956,7 +956,7 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
         Tmp2 != Node->getOperand(1))
       Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1,Tmp2);
     break;
-  
+
   case ISD::UREM:
   case ISD::SREM:
     Tmp1 = LegalizeOp(Node->getOperand(0));   // LHS
@@ -965,7 +965,7 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
     case TargetLowering::Legal:
       if (Tmp1 != Node->getOperand(0) ||
           Tmp2 != Node->getOperand(1))
-        Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1, 
+        Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1,
                              Tmp2);
       break;
     case TargetLowering::Promote:
@@ -1042,7 +1042,7 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
         // In the expand case, we must be dealing with a truncate, because
         // otherwise the result would be larger than the source.
         ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
-        
+
         // Since the result is legal, we should just be able to truncate the low
         // part of the source.
         Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Tmp1);
@@ -1134,7 +1134,7 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
         unsigned TySize = (unsigned)TLI.getTargetData().getTypeSize(Ty);
         unsigned Align  = TLI.getTargetData().getTypeAlignment(Ty);
         MachineFunction &MF = DAG.getMachineFunction();
-        int SSFI = 
+        int SSFI =
           MF.getFrameInfo()->CreateStackObject((unsigned)TySize, Align);
         SDOperand StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy());
         Result = DAG.getNode(ISD::TRUNCSTORE, MVT::Other, DAG.getEntryNode(),
@@ -1231,7 +1231,7 @@ SDOperand SelectionDAGLegalize::PromoteOp(SDOperand Op) {
     case Expand:
       ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
       // Truncate the low part of the expanded value to the result type
-      Result = DAG.getNode(ISD::TRUNCATE, VT, Tmp1); 
+      Result = DAG.getNode(ISD::TRUNCATE, VT, Tmp1);
     }
     break;
   case ISD::SIGN_EXTEND:
@@ -1445,7 +1445,7 @@ SDOperand SelectionDAGLegalize::PromoteOp(SDOperand Op) {
     // Insert the new chain mapping.
     AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
     break;
-  } 
+  }
   }
 
   assert(Result.Val && "Didn't set a result!");
@@ -1568,16 +1568,16 @@ bool SelectionDAGLegalize::ExpandShift(unsigned Opc, SDOperand Op,SDOperand Amt,
       return true;
     case ISD::SRA:
       if (Cst > VTBits) {
-        Hi = Lo = DAG.getNode(ISD::SRA, NVT, InH, 
+        Hi = Lo = DAG.getNode(ISD::SRA, NVT, InH,
                               DAG.getConstant(NVTBits-1, ShTy));
       } else if (Cst > NVTBits) {
-        Lo = DAG.getNode(ISD::SRA, NVT, InH, 
+        Lo = DAG.getNode(ISD::SRA, NVT, InH,
                            DAG.getConstant(Cst-NVTBits, ShTy));
-        Hi = DAG.getNode(ISD::SRA, NVT, InH, 
+        Hi = DAG.getNode(ISD::SRA, NVT, InH,
                               DAG.getConstant(NVTBits-1, ShTy));
       } else if (Cst == NVTBits) {
         Lo = InH;
-        Hi = DAG.getNode(ISD::SRA, NVT, InH, 
+        Hi = DAG.getNode(ISD::SRA, NVT, InH,
                               DAG.getConstant(NVTBits-1, ShTy));
       } else {
         Lo = DAG.getNode(ISD::OR, NVT,
@@ -1620,7 +1620,7 @@ bool SelectionDAGLegalize::ExpandShift(unsigned Opc, SDOperand Op,SDOperand Amt,
                                DAG.getNode(ISD::SHL, NVT, InH, ShAmt),
                                DAG.getNode(ISD::SRL, NVT, InL, NAmt));
     SDOperand T2 = DAG.getNode(ISD::SHL, NVT, InL, ShAmt); // T2 = Lo << Amt&31
-    
+
     Hi = DAG.getNode(ISD::SELECT, NVT, Cond, T2, T1);
     Lo = DAG.getNode(ISD::SELECT, NVT, Cond, DAG.getConstant(0, NVT), T2);
   } else {
@@ -1705,14 +1705,14 @@ static SDNode *FindAdjCallStackUp(SDNode *Node) {
 
   if (Node->hasOneUse())  // Simple case, only has one user to check.
     return FindAdjCallStackUp(*Node->use_begin());
-  
+
   SDOperand TheChain(Node, Node->getNumValues()-1);
   assert(TheChain.getValueType() == MVT::Other && "Is not a token chain!");
-  
-  for (SDNode::use_iterator UI = Node->use_begin(), 
+
+  for (SDNode::use_iterator UI = Node->use_begin(),
          E = Node->use_end(); ; ++UI) {
     assert(UI != E && "Didn't find a user of the tokchain, no ADJCALLSTACKUP!");
-    
+
     // Make sure to only follow users of our token chain.
     SDNode *User = *UI;
     for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i)
@@ -1732,7 +1732,7 @@ static SDOperand FindInputOutputChains(SDNode *OpNode, SDNode *&OutChain,
   SDNode *LatestAdjCallStackUp = 0;
   FindLatestAdjCallStackDown(OpNode, LatestAdjCallStackDown);
   //std::cerr << "Found node: "; LatestAdjCallStackDown->dump(); std::cerr <<"\n";
-  
+
   // It is possible that no ISD::ADJCALLSTACKDOWN was found because there is no
   // previous call in the function.  LatestCallStackDown may in that case be
   // the entry node itself.  Do not attempt to find a matching ADJCALLSTACKUP
@@ -1742,12 +1742,12 @@ static SDOperand FindInputOutputChains(SDNode *OpNode, SDNode *&OutChain,
   else
     LatestAdjCallStackUp = Entry.Val;
   assert(LatestAdjCallStackUp && "NULL return from FindAdjCallStackUp");
-  
+
   SDNode *EarliestAdjCallStackUp = 0;
   FindEarliestAdjCallStackUp(OpNode, EarliestAdjCallStackUp);
 
   if (EarliestAdjCallStackUp) {
-    //std::cerr << "Found node: "; 
+    //std::cerr << "Found node: ";
     //EarliestAdjCallStackUp->dump(); std::cerr <<"\n";
   }
 
@@ -1775,7 +1775,7 @@ SDOperand SelectionDAGLegalize::ExpandLibCall(const char *Name, SDNode *Node,
     Args.push_back(std::make_pair(Node->getOperand(i), ArgTy));
   }
   SDOperand Callee = DAG.getExternalSymbol(Name, TLI.getPointerTy());
-  
+
   // We don't care about token chains for libcalls.  We just use the entry
   // node as our input and ignore the output chain.  This allows us to place
   // calls wherever we need them to satisfy data dependences.
@@ -1866,7 +1866,7 @@ ExpandIntToFP(bool isSigned, MVT::ValueType DestTy, SDOperand Source) {
   const Type *RetTy = MVT::getTypeForValueType(DestTy);
   return TLI.LowerCallTo(InChain, RetTy, false, Callee, Args, DAG).first;
 }
-                   
+
 
 
 /// ExpandOp - Expand the specified SDOperand into its two component pieces
@@ -1922,7 +1922,7 @@ void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){
     // Aggregate register values are always in consequtive pairs.
     Lo = DAG.getCopyFromReg(Reg, NVT, Node->getOperand(0));
     Hi = DAG.getCopyFromReg(Reg+1, NVT, Lo.getValue(1));
-    
+
     // Remember that we legalized the chain.
     AddLegalizedOperand(Op.getValue(1), Hi.getValue(1));
 
@@ -1953,7 +1953,7 @@ void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){
     // other one.
     SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
                                Hi.getValue(1));
-    
+
     // Remember that we legalized the chain.
     AddLegalizedOperand(Op.getValue(1), TF);
     if (!TLI.isLittleEndian())
@@ -2031,7 +2031,7 @@ void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){
     // The low part is just a sign extension of the input (which degenerates to
     // a copy).
     Lo = DAG.getNode(ISD::SIGN_EXTEND, NVT, In);
-    
+
     // The high part is obtained by SRA'ing all but one of the bits of the lo
     // part.
     unsigned LoSize = MVT::getSizeInBits(Lo.getValueType());
@@ -2054,7 +2054,7 @@ void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){
     // The low part is just a zero extension of the input (which degenerates to
     // a copy).
     Lo = DAG.getNode(ISD::ZERO_EXTEND, NVT, In);
-    
+
     // The high part is just a zero.
     Hi = DAG.getConstant(0, NVT);
     break;
@@ -2121,7 +2121,7 @@ void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){
     Lo = ExpandLibCall("__lshrdi3", Node, Hi);
     break;
 
-  case ISD::ADD: 
+  case ISD::ADD:
     ExpandByParts(ISD::ADD_PARTS, Node->getOperand(0), Node->getOperand(1),
                   Lo, Hi);
     break;
diff --git a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index 0bfd578f79..5b0c710635 100644
--- a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -1,10 +1,10 @@
 //===-- SelectionDAG.cpp - Implement the SelectionDAG data structures -----===//
-// 
+//
 //                     The LLVM Compiler Infrastructure
 //
 // This file was developed by the LLVM research group and is distributed under
 // the University of Illinois Open Source License. See LICENSE.TXT for details.
-// 
+//
 //===----------------------------------------------------------------------===//
 //
 // This implements the SelectionDAG class.
@@ -60,7 +60,7 @@ static bool isInvertibleForFree(SDOperand N) {
   if (isa<ConstantSDNode>(N.Val)) return true;
   if (isa<SetCCSDNode>(N.Val) && N.Val->hasOneUse())
     return true;
-  return false;  
+  return false;
 }
 
 
@@ -118,9 +118,9 @@ ISD::CondCode ISD::getSetCCOrOperation(ISD::CondCode Op1, ISD::CondCode Op2,
   if (isInteger && (isSignedOp(Op1) | isSignedOp(Op2)) == 3)
     // Cannot fold a signed integer setcc with an unsigned integer setcc.
     return ISD::SETCC_INVALID;
-  
+
   unsigned Op = Op1 | Op2;  // Combine all of the condition bits.
-  
+
   // If the N and U bits get set then the resultant comparison DOES suddenly
   // care about orderedness, and is true when ordered.
   if (Op > ISD::SETTRUE2)
@@ -136,7 +136,7 @@ ISD::CondCode ISD::getSetCCAndOperation(ISD::CondCode Op1, ISD::CondCode Op2,
                                         bool isInteger) {
   if (isInteger && (isSignedOp(Op1) | isSignedOp(Op2)) == 3)
     // Cannot fold a signed setcc with an unsigned setcc.
-    return ISD::SETCC_INVALID; 
+    return ISD::SETCC_INVALID;
 
   // Combine all of the condition bits.
   return ISD::CondCode(Op1 & Op2);
@@ -269,7 +269,7 @@ void SelectionDAG::DeleteNodeIfDead(SDNode *N, void *NodeSet) {
     // Now that we removed this operand, see if there are no uses of it left.
     DeleteNodeIfDead(O, NodeSet);
   }
-  
+
   // Remove the node from the nodes set and delete it.
   std::set<SDNode*> &AllNodeSet = *(std::set<SDNode*>*)NodeSet;
   AllNodeSet.erase(N);
@@ -297,7 +297,7 @@ SDOperand SelectionDAG::getConstant(uint64_t Val, MVT::ValueType VT) {
   // Mask out any bits that are not valid for this constant.
   if (VT != MVT::i64)
     Val &= ((uint64_t)1 << MVT::getSizeInBits(VT)) - 1;
-  
+
   SDNode *&N = Constants[std::make_pair(Val, VT)];
   if (N) return SDOperand(N, 0);
   N = new ConstantSDNode(Val, VT);
@@ -317,7 +317,7 @@ SDOperand SelectionDAG::getConstantFP(double Val, MVT::ValueType VT) {
     double DV;
     uint64_t IV;
   };
-  
+
   DV = Val;
 
   SDNode *&N = ConstantFPs[std::make_pair(IV, VT)];
@@ -385,7 +385,7 @@ SDOperand SelectionDAG::getSetCC(ISD::CondCode Cond, MVT::ValueType VT,
     uint64_t C2 = N2C->getValue();
     if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val)) {
       uint64_t C1 = N1C->getValue();
-      
+
       // Sign extend the operands if required
       if (ISD::isSignedIntSetCC(Cond)) {
         C1 = N1C->getSignExtended();
@@ -480,14 +480,14 @@ SDOperand SelectionDAG::getSetCC(ISD::CondCode Cond, MVT::ValueType VT,
         N2 = getConstant(C2, N2.getValueType());
         N2C = cast<ConstantSDNode>(N2.Val);
       }
-      
+
       if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C2 == MinVal)
         return getConstant(0, VT);      // X < MIN --> false
-        
+
       // Canonicalize setgt X, Min --> setne X, Min
       if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C2 == MinVal)
         return getSetCC(ISD::SETNE, VT, N1, N2);
-        
+
       // If we have setult X, 1, turn it into seteq X, 0
       if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C2 == MinVal+1)
         return getSetCC(ISD::SETEQ, VT, N1,
@@ -538,7 +538,7 @@ SDOperand SelectionDAG::getSetCC(ISD::CondCode Cond, MVT::ValueType VT,
   if (ConstantFPSDNode *N1C = dyn_cast<ConstantFPSDNode>(N1.Val))
     if (ConstantFPSDNode *N2C = dyn_cast<ConstantFPSDNode>(N2.Val)) {
       double C1 = N1C->getValue(), C2 = N2C->getValue();
-      
+
       switch (Cond) {
       default: break; // FIXME: Implement the rest of these!
       case ISD::SETEQ:  return getConstant(C1 == C2, VT);
@@ -588,7 +588,7 @@ SDOperand SelectionDAG::getSetCC(ISD::CondCode Cond, MVT::ValueType VT,
       }
 
       // FIXME: move this stuff to the DAG Combiner when it exists!
-      
+
       // Simplify (X+Z) == X -->  Z == 0
       if (N1.getOperand(0) == N2)
         return getSetCC(Cond, VT, N1.getOperand(1),
@@ -601,7 +601,7 @@ SDOperand SelectionDAG::getSetCC(ISD::CondCode Cond, MVT::ValueType VT,
           assert(N1.getOpcode() == ISD::SUB && "Unexpected operation!");
           // (Z-X) == X  --> Z == X<<1
           return getSetCC(Cond, VT, N1.getOperand(0),
-                          getNode(ISD::SHL, N2.getValueType(), 
+                          getNode(ISD::SHL, N2.getValueType(),
                                   N2, getConstant(1, TLI.getShiftAmountTy())));
         }
       }
@@ -760,7 +760,7 @@ static bool MaskedValueIsZero(const SDOperand &Op, uint64_t Mask,
                               const TargetLowering &TLI) {
   unsigned SrcBits;
   if (Mask == 0) return true;
-  
+
   // If we know the result of a setcc has the top bits zero, use this info.
   switch (Op.getOpcode()) {
   case ISD::UNDEF:
@@ -769,7 +769,7 @@ static bool MaskedValueIsZero(const SDOperand &Op, uint64_t Mask,
     return (cast<ConstantSDNode>(Op)->getValue() & Mask) == 0;
 
   case ISD::SETCC:
-    return ((Mask & 1) == 0) && 
+    return ((Mask & 1) == 0) &&
            TLI.getSetCCResultContents() == TargetLowering::ZeroOrOneSetCCResult;
 
   case ISD::ZEXTLOAD:
@@ -1066,7 +1066,7 @@ SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT,
             Op2 == LHS->getCondition() && MVT::isInteger(LL.getValueType())) {
           if ((Op2 == ISD::SETEQ && Opcode == ISD::AND) ||
               (Op2 == ISD::SETNE && Opcode == ISD::OR))
-            return getSetCC(Op2, VT, 
+            return getSetCC(Op2, VT,
                             getNode(ISD::OR, LR.getValueType(), LL, RL), LR);
         }
 
@@ -1075,7 +1075,7 @@ SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT,
           Op2 = ISD::getSetCCSwappedOperands(Op2);
           goto MatchedBackwards;
         }
-      
+
         if (LL == RL && LR == RR) {
         MatchedBackwards:
           ISD::CondCode Result;
@@ -1179,7 +1179,7 @@ SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT,
     if (N1C)
       if (N1C->getValue())
         return N2;             // select true, X, Y -> X
-      else 
+      else
         return N3;             // select false, X, Y -> Y
 
     if (N2 == N3) return N2;   // select C, X, X -> X
@@ -1275,7 +1275,7 @@ SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT,
 
   SDNode *N = new SDNode(Opcode, N1, N2, N3);
   switch (Opcode) {
-  default: 
+  default:
     N->setValueTypes(VT);
     break;
   case ISD::DYNAMIC_STACKALLOC: // DYNAMIC_STACKALLOC produces pointer and chain
@@ -1371,7 +1371,7 @@ SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT,SDOperand N1,
     // If we are extending the result of a setcc, and we already know the
     // contents of the top bits, eliminate the extension.
     if (N1.getOpcode() == ISD::SETCC &&
-        TLI.getSetCCResultContents() == 
+        TLI.getSetCCResultContents() ==
                         TargetLowering::ZeroOrNegativeOneSetCCResult)
       return N1;
 
@@ -1412,7 +1412,7 @@ SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT,SDOperand N1,
     if (VT == EVT)
       return getNode(ISD::LOAD, VT, N1, N2);
     assert(EVT < VT && "Should only be an extending load, not truncating!");
-    assert((Opcode == ISD::EXTLOAD || MVT::isInteger(VT)) && 
+    assert((Opcode == ISD::EXTLOAD || MVT::isInteger(VT)) &&
            "Cannot sign/zero extend a FP load!");
     assert(MVT::isInteger(VT) == MVT::isInteger(EVT) &&
            "Cannot convert from FP to Int or Int -> FP!");
@@ -1444,7 +1444,7 @@ SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT,SDOperand N1,
     if (isa<Constant>(N1)) {
       SDOperand Op = getNode(ISD::TRUNCATE, EVT, N1);
       if (isa<Constant>(Op))
-        N1 = Op;      
+        N1 = Op;
     }
     // Also for ConstantFP?
 #endif
@@ -1599,8 +1599,8 @@ const char *SDNode::getOperationName() const {
     case ISD::SETOLT:  return "setcc:setolt";
     case ISD::SETOLE:  return "setcc:setole";
     case ISD::SETONE:  return "setcc:setone";
-      
-    case ISD::SETO:    return "setcc:seto"; 
+
+    case ISD::SETO:    return "setcc:seto";
     case ISD::SETUO:   return "setcc:setuo";
     case ISD::SETUEQ:  return "setcc:setue";
     case ISD::SETUGT:  return "setcc:setugt";
@@ -1608,7 +1608,7 @@ const char *SDNode::getOperationName() const {
     case ISD::SETULT:  return "setcc:setult";
     case ISD::SETULE:  return "setcc:setule";
     case ISD::SETUNE:  return "setcc:setune";
-      
+
     case ISD::SETEQ:   return "setcc:seteq";
     case ISD::SETGT:   return "setcc:setgt";
     case ISD::SETGE:   return "setcc:setge";
@@ -1643,7 +1643,7 @@ void SDNode::dump() const {
     std::cerr << "<" << CSDN->getValue() << ">";
   } else if (const ConstantFPSDNode *CSDN = dyn_cast<ConstantFPSDNode>(this)) {
     std::cerr << "<" << CSDN->getValue() << ">";
-  } else if (const GlobalAddressSDNode *GADN = 
+  } else if (const GlobalAddressSDNode *GADN =
              dyn_cast<GlobalAddressSDNode>(this)) {
     std::cerr << "<";
     WriteAsOperand(std::cerr, GADN->getGlobal()) << ">";
@@ -1652,7 +1652,7 @@ void SDNode::dump() const {
     std::cerr << "<" << FIDN->getIndex() << ">";
   } else if (const ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(this)){
     std::cerr << "<" << CP->getIndex() << ">";
-  } else if (const BasicBlockSDNode *BBDN = 
+  } else if (const BasicBlockSDNode *BBDN =
 	     dyn_cast<BasicBlockSDNode>(this)) {
     std::cerr << "<";
     const Value *LBB = (const Value*)BBDN->getBasicBlock()->getBasicBlock();
@@ -1676,7 +1676,7 @@ static void DumpNodes(SDNode *N, unsigned indent) {
     else
       std::cerr << "\n" << std::string(indent+2, ' ')
                 << (void*)N->getOperand(i).Val << ": <multiple use>";
-    
+
 
   std::cerr << "\n" << std::string(indent, ' ');
   N->dump();
diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
index f041905bb3..62376e5470 100644
--- a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
+++ b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
@@ -1,10 +1,10 @@
 //===-- SelectionDAGISel.cpp - Implement the SelectionDAGISel class -------===//
-// 
+//
 //                     The LLVM Compiler Infrastructure
 //
 // This file was developed by the LLVM research group and is distributed under
 // the University of Illinois Open Source License. See LICENSE.TXT for details.
-// 
+//
 //===----------------------------------------------------------------------===//
 //
 // This implements the SelectionDAGISel class.
@@ -79,7 +79,7 @@ namespace llvm {
     unsigned MakeReg(MVT::ValueType VT) {
       return RegMap->createVirtualRegister(TLI.getRegClassFor(VT));
     }
-  
+
     unsigned CreateRegForValue(const Value *V) {
       MVT::ValueType VT = TLI.getValueType(V->getType());
       // The common case is that we will only create one register for this
@@ -89,19 +89,19 @@ namespace llvm {
         // If we are promoting this value, pick the next largest supported type.
         return MakeReg(TLI.getTypeToTransformTo(VT));
       }
-    
+
       // If this value is represented with multiple target registers, make sure
       // to create enough consequtive registers of the right (smaller) type.
       unsigned NT = VT-1;  // Find the type to use.
       while (TLI.getNumElements((MVT::ValueType)NT) != 1)
         --NT;
-    
+
       unsigned R = MakeReg((MVT::ValueType)NT);
       for (unsigned i = 1; i != NV; ++i)
         MakeReg((MVT::ValueType)NT);
       return R;
     }
-  
+
     unsigned InitializeRegForValue(const Value *V) {
       unsigned &R = ValueMap[V];
       assert(R == 0 && "Already initialized this value register!");
@@ -122,7 +122,7 @@ static bool isUsedOutsideOfDefiningBlock(Instruction *I) {
 }
 
 FunctionLoweringInfo::FunctionLoweringInfo(TargetLowering &tli,
-                                           Function &fn, MachineFunction &mf) 
+                                           Function &fn, MachineFunction &mf)
     : TLI(tli), Fn(fn), MF(mf), RegMap(MF.getSSARegMap()) {
 
   // Initialize the mapping of values to registers.  This is only set up for
@@ -206,7 +206,7 @@ public:
   FunctionLoweringInfo &FuncInfo;
 
   SelectionDAGLowering(SelectionDAG &dag, TargetLowering &tli,
-                       FunctionLoweringInfo &funcinfo) 
+                       FunctionLoweringInfo &funcinfo)
     : TLI(tli), DAG(dag), TD(DAG.getTarget().getTargetData()),
       FuncInfo(funcinfo) {
   }
@@ -216,7 +216,7 @@ public:
   SDOperand getRoot() {
     if (PendingLoads.empty())
       return DAG.getRoot();
-    
+
     if (PendingLoads.size() == 1) {
       SDOperand Root = PendingLoads[0];
       DAG.setRoot(Root);
@@ -558,7 +558,7 @@ void SelectionDAGLowering::visitGetElementPtr(User &I) {
           IdxN = DAG.getNode(ISD::TRUNCATE, Scale.getValueType(), IdxN);
 
         IdxN = DAG.getNode(ISD::MUL, N.getValueType(), IdxN, Scale);
-			   
+			
         N = DAG.getNode(ISD::ADD, N.getValueType(), N, IdxN);
       }
     }
@@ -615,7 +615,7 @@ void SelectionDAGLowering::visitAlloca(AllocaInst &I) {
 
 void SelectionDAGLowering::visitLoad(LoadInst &I) {
   SDOperand Ptr = getValue(I.getOperand(0));
-  
+
   SDOperand Root;
   if (I.isVolatile())
     Root = getRoot();
@@ -672,7 +672,7 @@ void SelectionDAGLowering::visitCall(CallInst &I) {
       case Intrinsic::memcpy:  visitMemIntrinsic(I, ISD::MEMCPY); return;
       case Intrinsic::memset:  visitMemIntrinsic(I, ISD::MEMSET); return;
       case Intrinsic::memmove: visitMemIntrinsic(I, ISD::MEMMOVE); return;
-        
+
       case Intrinsic::isunordered:
         setValue(&I, DAG.getSetCC(ISD::SETUO, MVT::i1,getValue(I.getOperand(1)),
                                   getValue(I.getOperand(2))));
@@ -683,23 +683,23 @@ void SelectionDAGLowering::visitCall(CallInst &I) {
         return;
       }
       }
-  
+
   SDOperand Callee;
   if (!RenameFn)
     Callee = getValue(I.getOperand(0));
   else
     Callee = DAG.getExternalSymbol(RenameFn, TLI.getPointerTy());
   std::vector<std::pair<SDOperand, const Type*> > Args;
-  
+
   for (unsigned i = 1, e = I.getNumOperands(); i != e; ++i) {
     Value *Arg = I.getOperand(i);
     SDOperand ArgNode = getValue(Arg);
     Args.push_back(std::make_pair(ArgNode, Arg->getType()));
   }
-  
+
   const PointerType *PT = cast<PointerType>(I.getCalledValue()->getType());
   const FunctionType *FTy = cast<FunctionType>(PT->getElementType());
-  
+
   std::pair<SDOperand,SDOperand> Result =
     TLI.LowerCallTo(getRoot(), I.getType(), FTy->isVarArg(), Callee, Args, DAG);
   if (I.getType() != Type::VoidTy)
@@ -726,7 +726,7 @@ void SelectionDAGLowering::visitMalloc(MallocInst &I) {
   Args.push_back(std::make_pair(Src, TLI.getTargetData().getIntPtrType()));
 
   std::pair<SDOperand,SDOperand> Result =
-    TLI.LowerCallTo(getRoot(), I.getType(), false, 
+    TLI.LowerCallTo(getRoot(), I.getType(), false,
                     DAG.getExternalSymbol("malloc", IntPtr),
                     Args, DAG);
   setValue(&I, Result.first);  // Pointers always fit in registers
@@ -784,7 +784,7 @@ void SelectionDAGLowering::visitVAStart(CallInst &I) {
 
 void SelectionDAGLowering::visitVAArg(VAArgInst &I) {
   std::pair<SDOperand,SDOperand> Result =
-    TLI.LowerVAArgNext(false, getRoot(), getValue(I.getOperand(0)), 
+    TLI.LowerVAArgNext(false, getRoot(), getValue(I.getOperand(0)),
                        I.getType(), DAG);
   setValue(&I, Result.first);
   DAG.setRoot(Result.second);
@@ -792,7 +792,7 @@ void SelectionDAGLowering::visitVAArg(VAArgInst &I) {
 
 void SelectionDAGLowering::visitVANext(VANextInst &I) {
   std::pair<SDOperand,SDOperand> Result =
-    TLI.LowerVAArgNext(true, getRoot(), getValue(I.getOperand(0)), 
+    TLI.LowerVAArgNext(true, getRoot(), getValue(I.getOperand(0)),
                        I.getArgType(), DAG);
   setValue(&I, Result.first);
   DAG.setRoot(Result.second);
@@ -861,7 +861,7 @@ bool SelectionDAGISel::runOnFunction(Function &Fn) {
 
   for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I)
     SelectBasicBlock(I, MF, FuncInfo);
-  
+
   return true;
 }
 
@@ -915,7 +915,7 @@ LowerArguments(BasicBlock *BB, SelectionDAGLowering &SDL,
            AI != E; ++AI,++a)
         if (!AI->use_empty()) {
           SDL.setValue(AI, Args[a]);
-          SDOperand Copy = 
+          SDOperand Copy =
             CopyValueToVirtualRegister(SDL, AI, FuncInfo.ValueMap[AI]);
           UnorderedChains.push_back(Copy);
         }
@@ -931,7 +931,7 @@ LowerArguments(BasicBlock *BB, SelectionDAGLowering &SDL,
                                                       std::make_pair(AI, a)));
           } else {
             SDL.setValue(AI, Args[a]);
-            SDOperand Copy = 
+            SDOperand Copy =
               CopyValueToVirtualRegister(SDL, AI, FuncInfo.ValueMap[AI]);
             UnorderedChains.push_back(Copy);
           }
@@ -948,12 +948,12 @@ LowerArguments(BasicBlock *BB, SelectionDAGLowering &SDL,
     if (BLAI != FuncInfo.BlockLocalArguments.end() && BLAI->first == BB) {
       // Lower the arguments into this block.
       std::vector<SDOperand> Args = TLI.LowerArguments(F, SDL.DAG);
-      
+
       // Set up the value mapping for the local arguments.
       for (; BLAI != FuncInfo.BlockLocalArguments.end() && BLAI->first == BB;
            ++BLAI)
         SDL.setValue(BLAI->second.first, Args[BLAI->second.second]);
-      
+
       // Any dead arguments will just be ignored here.
     }
   }
@@ -966,7 +966,7 @@ void SelectionDAGISel::BuildSelectionDAG(SelectionDAG &DAG, BasicBlock *LLVMBB,
   SelectionDAGLowering SDL(DAG, TLI, FuncInfo);
 
   std::vector<SDOperand> UnorderedChains;
-  
+
   // Lower any arguments needed in this block.
   LowerArguments(LLVMBB, SDL, UnorderedChains);
 
@@ -994,7 +994,7 @@ void SelectionDAGISel::BuildSelectionDAG(SelectionDAG &DAG, BasicBlock *LLVMBB,
   // directly add them, because expansion might result in multiple MBB's for one
   // BB.  As such, the start of the BB might correspond to a different MBB than
   // the end.
-  // 
+  //
 
   // Emit constants only once even if used by multiple PHI nodes.
   std::map<Constant*, unsigned> ConstantsOut;
@@ -1026,7 +1026,7 @@ void SelectionDAGISel::BuildSelectionDAG(SelectionDAG &DAG, BasicBlock *LLVMBB,
         } else {
           Reg = FuncInfo.ValueMap[PHIOp];
           if (Reg == 0) {
-            assert(isa<AllocaInst>(PHIOp) && 
+            assert(isa<AllocaInst>(PHIOp) &&
                    FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) &&
                    "Didn't codegen value into a register!??");
             Reg = FuncInfo.CreateRegForValue(PHIOp);
@@ -1034,7 +1034,7 @@ void SelectionDAGISel::BuildSelectionDAG(SelectionDAG &DAG, BasicBlock *LLVMBB,
                              CopyValueToVirtualRegister(SDL, PHIOp, Reg));
           }
         }
-        
+
         // Remember that this register needs to added to the machine PHI node as
         // the input for this MBB.
         unsigned NumElements =
diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp b/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp
index b2e0cb761f..e3304f44be 100644
--- a/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp
+++ b/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp
@@ -1,10 +1,10 @@
 //===-- SelectionDAGPrinter.cpp - Implement SelectionDAG::viewGraph() -----===//
-// 
+//
 //                     The LLVM Compiler Infrastructure
 //
 // This file was developed by the LLVM research group and is distributed under
 // the University of Illinois Open Source License. See LICENSE.TXT for details.
-// 
+//
 //===----------------------------------------------------------------------===//
 //
 // This implements the SelectionDAG::viewGraph method.
@@ -70,7 +70,7 @@ std::string DOTGraphTraits<SelectionDAG*>::getNodeLabel(const SDNode *Node,
     Op += ": " + utostr(CSDN->getValue());
   } else if (const ConstantFPSDNode *CSDN = dyn_cast<ConstantFPSDNode>(Node)) {
     Op += ": " + ftostr(CSDN->getValue());
-  } else if (const GlobalAddressSDNode *GADN = 
+  } else if (const GlobalAddressSDNode *GADN =
              dyn_cast<