Split the SelectionDAG-building code, including the FunctionLoweringInfo

and SelectionDAGLowering classes, out of SelectionDAGISel.cpp and put
it in a separate file, SelectionDAGBuild.cpp.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55701 91177308-0d34-0410-b5e6-96231b3b80d8

1 files changed, 6 insertions, 5134 deletions

diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
index f242094baf..a2cf6a1b56 100644
--- a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
+++ b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
@@ -13,6 +13,7 @@
 
 #define DEBUG_TYPE "isel"
 #include "llvm/CodeGen/SelectionDAGISel.h"
+#include "SelectionDAGBuild.h"
 #include "llvm/ADT/BitVector.h"
 #include "llvm/Analysis/AliasAnalysis.h"
 #include "llvm/Constants.h"
@@ -118,175 +119,6 @@ static RegisterScheduler
 defaultListDAGScheduler("default", "  Best scheduler for the target",
                         createDefaultScheduler);
 
-namespace { struct SDISelAsmOperandInfo; }
-
-/// ComputeLinearIndex - Given an LLVM IR aggregate type and a sequence
-/// insertvalue or extractvalue indices that identify a member, return
-/// the linearized index of the start of the member.
-///
-static unsigned ComputeLinearIndex(const TargetLowering &TLI, const Type *Ty,
-                                   const unsigned *Indices,
-                                   const unsigned *IndicesEnd,
-                                   unsigned CurIndex = 0) {
-  // Base case: We're done.
-  if (Indices && Indices == IndicesEnd)
-    return CurIndex;
-
-  // Given a struct type, recursively traverse the elements.
-  if (const StructType *STy = dyn_cast<StructType>(Ty)) {
-    for (StructType::element_iterator EB = STy->element_begin(),
-                                      EI = EB,
-                                      EE = STy->element_end();
-        EI != EE; ++EI) {
-      if (Indices && *Indices == unsigned(EI - EB))
-        return ComputeLinearIndex(TLI, *EI, Indices+1, IndicesEnd, CurIndex);
-      CurIndex = ComputeLinearIndex(TLI, *EI, 0, 0, CurIndex);
-    }
-  }
-  // Given an array type, recursively traverse the elements.
-  else if (const ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
-    const Type *EltTy = ATy->getElementType();
-    for (unsigned i = 0, e = ATy->getNumElements(); i != e; ++i) {
-      if (Indices && *Indices == i)
-        return ComputeLinearIndex(TLI, EltTy, Indices+1, IndicesEnd, CurIndex);
-      CurIndex = ComputeLinearIndex(TLI, EltTy, 0, 0, CurIndex);
-    }
-  }
-  // We haven't found the type we're looking for, so keep searching.
-  return CurIndex + 1;
-}
-
-/// ComputeValueVTs - Given an LLVM IR type, compute a sequence of
-/// MVTs that represent all the individual underlying
-/// non-aggregate types that comprise it.
-///
-/// If Offsets is non-null, it points to a vector to be filled in
-/// with the in-memory offsets of each of the individual values.
-///
-static void ComputeValueVTs(const TargetLowering &TLI, const Type *Ty,
-                            SmallVectorImpl<MVT> &ValueVTs,
-                            SmallVectorImpl<uint64_t> *Offsets = 0,
-                            uint64_t StartingOffset = 0) {
-  // Given a struct type, recursively traverse the elements.
-  if (const StructType *STy = dyn_cast<StructType>(Ty)) {
-    const StructLayout *SL = TLI.getTargetData()->getStructLayout(STy);
-    for (StructType::element_iterator EB = STy->element_begin(),
-                                      EI = EB,
-                                      EE = STy->element_end();
-         EI != EE; ++EI)
-      ComputeValueVTs(TLI, *EI, ValueVTs, Offsets,
-                      StartingOffset + SL->getElementOffset(EI - EB));
-    return;
-  }
-  // Given an array type, recursively traverse the elements.
-  if (const ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
-    const Type *EltTy = ATy->getElementType();
-    uint64_t EltSize = TLI.getTargetData()->getABITypeSize(EltTy);
-    for (unsigned i = 0, e = ATy->getNumElements(); i != e; ++i)
-      ComputeValueVTs(TLI, EltTy, ValueVTs, Offsets,
-                      StartingOffset + i * EltSize);
-    return;
-  }
-  // Base case: we can get an MVT for this LLVM IR type.
-  ValueVTs.push_back(TLI.getValueType(Ty));
-  if (Offsets)
-    Offsets->push_back(StartingOffset);
-}
-
-namespace {
-  /// RegsForValue - This struct represents the registers (physical or virtual)
-  /// that a particular set of values is assigned, and the type information about
-  /// the value. The most common situation is to represent one value at a time,
-  /// but struct or array values are handled element-wise as multiple values.
-  /// The splitting of aggregates is performed recursively, so that we never
-  /// have aggregate-typed registers. The values at this point do not necessarily
-  /// have legal types, so each value may require one or more registers of some
-  /// legal type.
-  /// 
-  struct VISIBILITY_HIDDEN RegsForValue {
-    /// TLI - The TargetLowering object.
-    ///
-    const TargetLowering *TLI;
-
-    /// ValueVTs - The value types of the values, which may not be legal, and
-    /// may need be promoted or synthesized from one or more registers.
-    ///
-    SmallVector<MVT, 4> ValueVTs;
-    
-    /// RegVTs - The value types of the registers. This is the same size as
-    /// ValueVTs and it records, for each value, what the type of the assigned
-    /// register or registers are. (Individual values are never synthesized
-    /// from more than one type of register.)
-    ///
-    /// With virtual registers, the contents of RegVTs is redundant with TLI's
-    /// getRegisterType member function, however when with physical registers
-    /// it is necessary to have a separate record of the types.
-    ///
-    SmallVector<MVT, 4> RegVTs;
-    
-    /// Regs - This list holds the registers assigned to the values.
-    /// Each legal or promoted value requires one register, and each
-    /// expanded value requires multiple registers.
-    ///
-    SmallVector<unsigned, 4> Regs;
-    
-    RegsForValue() : TLI(0) {}
-    
-    RegsForValue(const TargetLowering &tli,
-                 const SmallVector<unsigned, 4> &regs, 
-                 MVT regvt, MVT valuevt)
-      : TLI(&tli),  ValueVTs(1, valuevt), RegVTs(1, regvt), Regs(regs) {}
-    RegsForValue(const TargetLowering &tli,
-                 const SmallVector<unsigned, 4> &regs, 
-                 const SmallVector<MVT, 4> &regvts,
-                 const SmallVector<MVT, 4> &valuevts)
-      : TLI(&tli), ValueVTs(valuevts), RegVTs(regvts), Regs(regs) {}
-    RegsForValue(const TargetLowering &tli,
-                 unsigned Reg, const Type *Ty) : TLI(&tli) {
-      ComputeValueVTs(tli, Ty, ValueVTs);
-
-      for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) {
-        MVT ValueVT = ValueVTs[Value];
-        unsigned NumRegs = TLI->getNumRegisters(ValueVT);
-        MVT RegisterVT = TLI->getRegisterType(ValueVT);
-        for (unsigned i = 0; i != NumRegs; ++i)
-          Regs.push_back(Reg + i);
-        RegVTs.push_back(RegisterVT);
-        Reg += NumRegs;
-      }
-    }
-    
-    /// append - Add the specified values to this one.
-    void append(const RegsForValue &RHS) {
-      TLI = RHS.TLI;
-      ValueVTs.append(RHS.ValueVTs.begin(), RHS.ValueVTs.end());
-      RegVTs.append(RHS.RegVTs.begin(), RHS.RegVTs.end());
-      Regs.append(RHS.Regs.begin(), RHS.Regs.end());
-    }
-    
-    
-    /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
-    /// this value and returns the result as a ValueVTs value.  This uses 
-    /// Chain/Flag as the input and updates them for the output Chain/Flag.
-    /// If the Flag pointer is NULL, no flag is used.
-    SDValue getCopyFromRegs(SelectionDAG &DAG,
-                              SDValue &Chain, SDValue *Flag) const;
-
-    /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
-    /// specified value into the registers specified by this object.  This uses 
-    /// Chain/Flag as the input and updates them for the output Chain/Flag.
-    /// If the Flag pointer is NULL, no flag is used.
-    void getCopyToRegs(SDValue Val, SelectionDAG &DAG,
-                       SDValue &Chain, SDValue *Flag) const;
-    
-    /// AddInlineAsmOperands - Add this value to the specified inlineasm node
-    /// operand list.  This adds the code marker and includes the number of 
-    /// values added into it.
-    void AddInlineAsmOperands(unsigned Code, SelectionDAG &DAG,
-                              std::vector<SDValue> &Ops) const;
-  };
-}
-
 namespace llvm {
   //===--------------------------------------------------------------------===//
   /// createDefaultScheduler - This creates an instruction scheduler appropriate
@@ -305,4548 +137,6 @@ namespace llvm {
       return createBURRListDAGScheduler(IS, DAG, BB, Fast);
     }
   }
-
-
-  //===--------------------------------------------------------------------===//
-  /// FunctionLoweringInfo - This contains information that is global to a
-  /// function that is used when lowering a region of the function.
-  class FunctionLoweringInfo {
-  public:
-    TargetLowering &TLI;
-    Function *Fn;
-    MachineFunction *MF;
-    MachineRegisterInfo *RegInfo;
-
-    explicit FunctionLoweringInfo(TargetLowering &TLI);
-
-    /// set - Initialize this FunctionLoweringInfo with the given Function
-    /// and its associated MachineFunction.
-    ///
-    void set(Function &Fn, MachineFunction &MF);
-
-    /// MBBMap - A mapping from LLVM basic blocks to their machine code entry.
-    DenseMap<const BasicBlock*, MachineBasicBlock *> MBBMap;
-
-    /// ValueMap - Since we emit code for the function a basic block at a time,
-    /// we must remember which virtual registers hold the values for
-    /// cross-basic-block values.
-    DenseMap<const Value*, unsigned> ValueMap;
-
-    /// StaticAllocaMap - Keep track of frame indices for fixed sized allocas in
-    /// the entry block.  This allows the allocas to be efficiently referenced
-    /// anywhere in the function.
-    DenseMap<const AllocaInst*, int> StaticAllocaMap;
-
-#ifndef NDEBUG
-    SmallSet<Instruction*, 8> CatchInfoLost;
-    SmallSet<Instruction*, 8> CatchInfoFound;
-#endif
-
-    unsigned MakeReg(MVT VT) {
-      return RegInfo->createVirtualRegister(TLI.getRegClassFor(VT));
-    }
-    
-    /// isExportedInst - Return true if the specified value is an instruction
-    /// exported from its block.
-    bool isExportedInst(const Value *V) {
-      return ValueMap.count(V);
-    }
-
-    unsigned CreateRegForValue(const Value *V);
-    
-    unsigned InitializeRegForValue(const Value *V) {
-      unsigned &R = ValueMap[V];
-      assert(R == 0 && "Already initialized this value register!");
-      return R = CreateRegForValue(V);
-    }
-    
-    struct LiveOutInfo {
-      unsigned NumSignBits;
-      APInt KnownOne, KnownZero;
-      LiveOutInfo() : NumSignBits(0) {}
-    };
-    
-    /// LiveOutRegInfo - Information about live out vregs, indexed by their
-    /// register number offset by 'FirstVirtualRegister'.
-    std::vector<LiveOutInfo> LiveOutRegInfo;
-
-    /// clear - Clear out all the function-specific state. This returns this
-    /// FunctionLoweringInfo to an empty state, ready to be used for a
-    /// different function.
-    void clear() {
-      MBBMap.clear();
-      ValueMap.clear();
-      StaticAllocaMap.clear();
-#ifndef NDEBUG
-      CatchInfoLost.clear();
-      CatchInfoFound.clear();
-#endif
-      LiveOutRegInfo.clear();
-    }
-  };
-}
-
-/// isSelector - Return true if this instruction is a call to the
-/// eh.selector intrinsic.
-static bool isSelector(Instruction *I) {
-  if (IntrinsicInst *II = dyn_cast<IntrinsicInst>(I))
-    return (II->getIntrinsicID() == Intrinsic::eh_selector_i32 ||
-            II->getIntrinsicID() == Intrinsic::eh_selector_i64);
-  return false;
-}
-
-/// isUsedOutsideOfDefiningBlock - Return true if this instruction is used by
-/// PHI nodes or outside of the basic block that defines it, or used by a 
-/// switch or atomic instruction, which may expand to multiple basic blocks.
-static bool isUsedOutsideOfDefiningBlock(Instruction *I) {
-  if (isa<PHINode>(I)) return true;
-  BasicBlock *BB = I->getParent();
-  for (Value::use_iterator UI = I->use_begin(), E = I->use_end(); UI != E; ++UI)
-    if (cast<Instruction>(*UI)->getParent() != BB || isa<PHINode>(*UI) ||
-        // FIXME: Remove switchinst special case.
-        isa<SwitchInst>(*UI))
-      return true;
-  return false;
-}
-
-/// isOnlyUsedInEntryBlock - If the specified argument is only used in the
-/// entry block, return true.  This includes arguments used by switches, since
-/// the switch may expand into multiple basic blocks.
-static bool isOnlyUsedInEntryBlock(Argument *A) {
-  // With FastISel active, we may be splitting blocks, so force creation
-  // of virtual registers for all non-dead arguments.
-  if (EnableFastISel)
-    return A->use_empty();
-
-  BasicBlock *Entry = A->getParent()->begin();
-  for (Value::use_iterator UI = A->use_begin(), E = A->use_end(); UI != E; ++UI)
-    if (cast<Instruction>(*UI)->getParent() != Entry || isa<SwitchInst>(*UI))
-      return false;  // Use not in entry block.
-  return true;
-}
-
-FunctionLoweringInfo::FunctionLoweringInfo(TargetLowering &tli)
-  : TLI(tli) {
-}
-
-void FunctionLoweringInfo::set(Function &fn, MachineFunction &mf) {
-   Fn = &fn;
-   MF = &mf;
-   RegInfo = &MF->getRegInfo();
-
-  // Create a vreg for each argument register that is not dead and is used
-  // outside of the entry block for the function.
-  for (Function::arg_iterator AI = Fn->arg_begin(), E = Fn->arg_end();
-       AI != E; ++AI)
-    if (!isOnlyUsedInEntryBlock(AI))
-      InitializeRegForValue(AI);
-
-  // Initialize the mapping of values to registers.  This is only set up for
-  // instruction values that are used outside of the block that defines
-  // them.
-  Function::iterator BB = Fn->begin(), EB = Fn->end();
-  for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; ++I)
-    if (AllocaInst *AI = dyn_cast<AllocaInst>(I))
-      if (ConstantInt *CUI = dyn_cast<ConstantInt>(AI->getArraySize())) {
-        const Type *Ty = AI->getAllocatedType();
-        uint64_t TySize = TLI.getTargetData()->getABITypeSize(Ty);
-        unsigned Align = 
-          std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty),
-                   AI->getAlignment());
-
-        TySize *= CUI->getZExtValue();   // Get total allocated size.
-        if (TySize == 0) TySize = 1; // Don't create zero-sized stack objects.
-        StaticAllocaMap[AI] =
-          MF->getFrameInfo()->CreateStackObject(TySize, Align);
-      }
-
-  for (; BB != EB; ++BB)
-    for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; ++I)
-      if (!I->use_empty() && isUsedOutsideOfDefiningBlock(I))
-        if (!isa<AllocaInst>(I) ||
-            !StaticAllocaMap.count(cast<AllocaInst>(I)))
-          InitializeRegForValue(I);
-
-  // Create an initial MachineBasicBlock for each LLVM BasicBlock in F.  This
-  // also creates the initial PHI MachineInstrs, though none of the input
-  // operands are populated.
-  for (BB = Fn->begin(), EB = Fn->end(); BB != EB; ++BB) {
-    MachineBasicBlock *MBB = mf.CreateMachineBasicBlock(BB);
-    MBBMap[BB] = MBB;
-    MF->push_back(MBB);
-
-    // Create Machine PHI nodes for LLVM PHI nodes, lowering them as
-    // appropriate.
-    PHINode *PN;
-    for (BasicBlock::iterator I = BB->begin();(PN = dyn_cast<PHINode>(I)); ++I){
-      if (PN->use_empty()) continue;
-      
-      unsigned PHIReg = ValueMap[PN];
-      assert(PHIReg && "PHI node does not have an assigned virtual register!");
-
-      SmallVector<MVT, 4> ValueVTs;
-      ComputeValueVTs(TLI, PN->getType(), ValueVTs);
-      for (unsigned vti = 0, vte = ValueVTs.size(); vti != vte; ++vti) {
-        MVT VT = ValueVTs[vti];
-        unsigned NumRegisters = TLI.getNumRegisters(VT);
-        const TargetInstrInfo *TII = TLI.getTargetMachine().getInstrInfo();
-        for (unsigned i = 0; i != NumRegisters; ++i)
-          BuildMI(MBB, TII->get(TargetInstrInfo::PHI), PHIReg+i);
-        PHIReg += NumRegisters;
-      }
-    }
-  }
-}
-
-/// CreateRegForValue - Allocate the appropriate number of virtual registers of
-/// the correctly promoted or expanded types.  Assign these registers
-/// consecutive vreg numbers and return the first assigned number.
-///
-/// In the case that the given value has struct or array type, this function
-/// will assign registers for each member or element.
-///
-unsigned FunctionLoweringInfo::CreateRegForValue(const Value *V) {
-  SmallVector<MVT, 4> ValueVTs;
-  ComputeValueVTs(TLI, V->getType(), ValueVTs);
-
-  unsigned FirstReg = 0;
-  for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) {
-    MVT ValueVT = ValueVTs[Value];
-    MVT RegisterVT = TLI.getRegisterType(ValueVT);
-
-    unsigned NumRegs = TLI.getNumRegisters(ValueVT);
-    for (unsigned i = 0; i != NumRegs; ++i) {
-      unsigned R = MakeReg(RegisterVT);
-      if (!FirstReg) FirstReg = R;
-    }
-  }
-  return FirstReg;
-}
-
-//===----------------------------------------------------------------------===//
-/// SelectionDAGLowering - This is the common target-independent lowering
-/// implementation that is parameterized by a TargetLowering object.
-/// Also, targets can overload any lowering method.
-///
-namespace llvm {
-class SelectionDAGLowering {
-  MachineBasicBlock *CurMBB;
-
-  DenseMap<const Value*, SDValue> NodeMap;
-
-  /// PendingLoads - Loads are not emitted to the program immediately.  We bunch
-  /// them up and then emit token factor nodes when possible.  This allows us to
-  /// get simple disambiguation between loads without worrying about alias
-  /// analysis.
-  SmallVector<SDValue, 8> PendingLoads;
-
-  /// PendingExports - CopyToReg nodes that copy values to virtual registers
-  /// for export to other blocks need to be emitted before any terminator
-  /// instruction, but they have no other ordering requirements. We bunch them
-  /// up and the emit a single tokenfactor for them just before terminator
-  /// instructions.
-  SmallVector<SDValue, 8> PendingExports;
-
-  /// Case - A struct to record the Value for a switch case, and the
-  /// case's target basic block.
-  struct Case {
-    Constant* Low;
-    Constant* High;
-    MachineBasicBlock* BB;
-
-    Case() : Low(0), High(0), BB(0) { }
-    Case(Constant* low, Constant* high, MachineBasicBlock* bb) :
-      Low(low), High(high), BB(bb) { }
-    uint64_t size() const {
-      uint64_t rHigh = cast<ConstantInt>(High)->getSExtValue();
-      uint64_t rLow  = cast<ConstantInt>(Low)->getSExtValue();
-      return (rHigh - rLow + 1ULL);
-    }
-  };
-
-  struct CaseBits {
-    uint64_t Mask;
-    MachineBasicBlock* BB;
-    unsigned Bits;
-
-    CaseBits(uint64_t mask, MachineBasicBlock* bb, unsigned bits):
-      Mask(mask), BB(bb), Bits(bits) { }
-  };
-
-  typedef std::vector<Case>           CaseVector;
-  typedef std::vector<CaseBits>       CaseBitsVector;
-  typedef CaseVector::iterator        CaseItr;
-  typedef std::pair<CaseItr, CaseItr> CaseRange;
-
-  /// CaseRec - A struct with ctor used in lowering switches to a binary tree
-  /// of conditional branches.
-  struct CaseRec {
-    CaseRec(MachineBasicBlock *bb, Constant *lt, Constant *ge, CaseRange r) :
-    CaseBB(bb), LT(lt), GE(ge), Range(r) {}
-
-    /// CaseBB - The MBB in which to emit the compare and branch
-    MachineBasicBlock *CaseBB;
-    /// LT, GE - If nonzero, we know the current case value must be less-than or
-    /// greater-than-or-equal-to these Constants.
-    Constant *LT;
-    Constant *GE;
-    /// Range - A pair of iterators representing the range of case values to be
-    /// processed at this point in the binary search tree.
-    CaseRange Range;
-  };
-
-  typedef std::vector<CaseRec> CaseRecVector;
-
-  /// The comparison function for sorting the switch case values in the vector.
-  /// WARNING: Case ranges should be disjoint!
-  struct CaseCmp {
-    bool operator () (const Case& C1, const Case& C2) {
-      assert(isa<ConstantInt>(C1.Low) && isa<ConstantInt>(C2.High));
-      const ConstantInt* CI1 = cast<const ConstantInt>(C1.Low);
-      const ConstantInt* CI2 = cast<const ConstantInt>(C2.High);
-      return CI1->getValue().slt(CI2->getValue());
-    }
-  };
-
-  struct CaseBitsCmp {
-    bool operator () (const CaseBits& C1, const CaseBits& C2) {
-      return C1.Bits > C2.Bits;
-    }
-  };
-
-  unsigned Clusterify(CaseVector& Cases, const SwitchInst &SI);
-  
-  /// CaseBlock - This structure is used to communicate between SDLowering and
-  /// SDISel for the code generation of additional basic blocks needed by multi-
-  /// case switch statements.
-  struct CaseBlock {
-    CaseBlock(ISD::CondCode cc, Value *cmplhs, Value *cmprhs, Value *cmpmiddle,
-              MachineBasicBlock *truebb, MachineBasicBlock *falsebb,
-              MachineBasicBlock *me)
-      : CC(cc), CmpLHS(cmplhs), CmpMHS(cmpmiddle), CmpRHS(cmprhs),
-        TrueBB(truebb), FalseBB(falsebb), ThisBB(me) {}
-    // CC - the condition code to use for the case block's setcc node
-    ISD::CondCode CC;
-    // CmpLHS/CmpRHS/CmpMHS - The LHS/MHS/RHS of the comparison to emit.
-    // Emit by default LHS op RHS. MHS is used for range comparisons:
-    // If MHS is not null: (LHS <= MHS) and (MHS <= RHS).
-    Value *CmpLHS, *CmpMHS, *CmpRHS;
-    // TrueBB/FalseBB - the block to branch to if the setcc is true/false.
-    MachineBasicBlock *TrueBB, *FalseBB;
-    // ThisBB - the block into which to emit the code for the setcc and branches
-    MachineBasicBlock *ThisBB;
-  };
-  struct JumpTable {
-    JumpTable(unsigned R, unsigned J, MachineBasicBlock *M,
-              MachineBasicBlock *D): Reg(R), JTI(J), MBB(M), Default(D) {}
-  
-    /// Reg - the virtual register containing the index of the jump table entry
-    //. to jump to.
-    unsigned Reg;
-    /// JTI - the JumpTableIndex for this jump table in the function.
-    unsigned JTI;
-    /// MBB - the MBB into which to emit the code for the indirect jump.
-    MachineBasicBlock *MBB;
-    /// Default - the MBB of the default bb, which is a successor of the range
-    /// check MBB.  This is when updating PHI nodes in successors.
-    MachineBasicBlock *Default;
-  };
-  struct JumpTableHeader {
-    JumpTableHeader(uint64_t F, uint64_t L, Value* SV, MachineBasicBlock* H,
-                    bool E = false):
-      First(F), Last(L), SValue(SV), HeaderBB(H), Emitted(E) {}
-    uint64_t First;
-    uint64_t Last;
-    Value *SValue;
-    MachineBasicBlock *HeaderBB;
-    bool Emitted;
-  };
-  typedef std::pair<JumpTableHeader, JumpTable> JumpTableBlock;
-
-  struct BitTestCase {
-    BitTestCase(uint64_t M, MachineBasicBlock* T, MachineBasicBlock* Tr):
-      Mask(M), ThisBB(T), TargetBB(Tr) { }
-    uint64_t Mask;
-    MachineBasicBlock* ThisBB;
-    MachineBasicBlock* TargetBB;
-  };
-
-  typedef SmallVector<BitTestCase, 3> BitTestInfo;
-
-  struct BitTestBlock {
-    BitTestBlock(uint64_t F, uint64_t R, Value* SV,
-                 unsigned Rg, bool E,
-                 MachineBasicBlock* P, MachineBasicBlock* D,
-                 const BitTestInfo& C):
-      First(F), Range(R), SValue(SV), Reg(Rg), Emitted(E),
-      Parent(P), Default(D), Cases(C) { }
-    uint64_t First;
-    uint64_t Range;
-    Value  *SValue;
-    unsigned Reg;
-    bool Emitted;
-    MachineBasicBlock *Parent;
-    MachineBasicBlock *Default;
-    BitTestInfo Cases;
-  };
-
-public:
-  // TLI - This is information that describes the available target features we
-  // need for lowering.  This indicates when operations are unavailable,
-  // implemented with a libcall, etc.
-  TargetLowering &TLI;
-  SelectionDAG &DAG;
-  const TargetData *TD;
-  AliasAnalysis *AA;
-
-  /// SwitchCases - Vector of CaseBlock structures used to communicate
-  /// SwitchInst code generation information.
-  std::vector<CaseBlock> SwitchCases;
-  /// JTCases - Vector of JumpTable structures used to communicate
-  /// SwitchInst code generation information.
-  std::vector<JumpTableBlock> JTCases;
-  /// BitTestCases - Vector of BitTestBlock structures used to communicate
-  /// SwitchInst code generation information.
-  std::vector<BitTestBlock> BitTestCases;
-  
-  std::vector<std::pair<MachineInstr*, unsigned> > PHINodesToUpdate;
-
-  // Emit PHI-node-operand constants only once even if used by multiple
-  // PHI nodes.
-  DenseMap<Constant*, unsigned> ConstantsOut;
-
-  /// FuncInfo - Information about the function as a whole.
-  ///
-  FunctionLoweringInfo &FuncInfo;
-  
-  /// GFI - Garbage collection metadata for the function.
-  GCFunctionInfo *GFI;
-
-  SelectionDAGLowering(SelectionDAG &dag, TargetLowering &tli,
-                       FunctionLoweringInfo &funcinfo)
-    : TLI(tli), DAG(dag), FuncInfo(funcinfo) {
-  }
-
-  void init(GCFunctionInfo *gfi, AliasAnalysis &aa) {
-    AA = &aa;
-    GFI = gfi;
-    TD = DAG.getTarget().getTargetData();
-  }
-
-  /// clear - Clear out the curret SelectionDAG and the associated
-  /// state and prepare this SelectionDAGLowering object to be used
-  /// for a new block. This doesn't clear out information about
-  /// additional blocks that are needed to complete switch lowering
-  /// or PHI node updating; that information is cleared out as it is
-  /// consumed.
-  void clear() {
-    NodeMap.clear();
-    PendingLoads.clear();
-    PendingExports.clear();
-    DAG.clear();
-  }
-
-  /// getRoot - Return the current virtual root of the Selection DAG,
-  /// flushing any PendingLoad items. This must be done before emitting
-  /// a store or any other node that may need to be ordered after any
-  /// prior load instructions.
-  ///
-  SDValue getRoot() {
-    if (PendingLoads.empty())
-      return DAG.getRoot();
-
-    if (PendingLoads.size() == 1) {
-      SDValue Root = PendingLoads[0];
-      DAG.setRoot(Root);
-      PendingLoads.clear();
-      return Root;
-    }
-
-    // Otherwise, we have to make a token factor node.
-    SDValue Root = DAG.getNode(ISD::TokenFactor, MVT::Other,
-                                 &PendingLoads[0], PendingLoads.size());
-    PendingLoads.clear();
-    DAG.setRoot(Root);
-    return Root;
-  }
-
-  /// getControlRoot - Similar to getRoot, but instead of flushing all the
-  /// PendingLoad items, flush all the PendingExports items. It is necessary
-  /// to do this before emitting a terminator instruction.
-  ///
-  SDValue getControlRoot() {
-    SDValue Root = DAG.getRoot();
-
-    if (PendingExports.empty())
-      return Root;
-
-    // Turn all of the CopyToReg chains into one factored node.
-    if (Root.getOpcode() != ISD::EntryToken) {
-      unsigned i = 0, e = PendingExports.size();
-      for (; i != e; ++i) {
-        assert(PendingExports[i].getNode()->getNumOperands() > 1);
-        if (PendingExports[i].getNode()->getOperand(0) == Root)
-          break;  // Don't add the root if we already indirectly depend on it.
-      }
-        
-      if (i == e)
-        PendingExports.push_back(Root);
-    }
-
-    Root = DAG.getNode(ISD::TokenFactor, MVT::Other,
-                       &PendingExports[0],
-                       PendingExports.size());
-    PendingExports.clear();
-    DAG.setRoot(Root);
-    return Root;
-  }
-
-  void CopyValueToVirtualRegister(Value *V, unsigned Reg);
-
-  void visit(Instruction &I) { visit(I.getOpcode(), I); }
-
-  void visit(unsigned Opcode, User &I) {
-    // Note: this doesn't use InstVisitor, because it has to work with
-    // ConstantExpr's in addition to instructions.
-    switch (Opcode) {
-    default: assert(0 && "Unknown instruction type encountered!");
-             abort();
-      // Build the switch statement using the Instruction.def file.
-#define HANDLE_INST(NUM, OPCODE, CLASS) \
-    case Instruction::OPCODE:return visit##OPCODE((CLASS&)I);
-#include "llvm/Instruction.def"
-    }
-  }
-
-  void setCurrentBasicBlock(MachineBasicBlock *MBB) { CurMBB = MBB; }
-
-  SDValue getValue(const Value *V);
-
-  void setValue(const Value *V, SDValue NewN) {
-    SDValue &N = NodeMap[V];
-    assert(N.getNode() == 0 && "Already set a value for this node!");
-    N = NewN;
-  }
-  
-  void GetRegistersForValue(SDISelAsmOperandInfo &OpInfo, bool HasEarlyClobber,
-                            std::set<unsigned> &OutputRegs, 
-                            std::set<unsigned> &InputRegs);
-
-  void FindMergedConditions(Value *Cond, MachineBasicBlock *TBB,
-                            MachineBasicBlock *FBB, MachineBasicBlock *CurBB,
-                            unsigned Opc);
-  bool ShouldEmitAsBranches(const std::vector<CaseBlock> &Cases);
-  bool isExportableFromCurrentBlock(Value *V, const BasicBlock *FromBB);
-  void ExportFromCurrentBlock(Value *V);
-  void LowerCallTo(CallSite CS, SDValue Callee, bool IsTailCall,
-                   MachineBasicBlock *LandingPad = NULL);
-
-  // Terminator instructions.
-  void visitRet(ReturnInst &I);
-  void visitBr(BranchInst &I);
-  void visitSwitch(SwitchInst &I);
-  void visitUnreachable(UnreachableInst &I) { /* noop */ }
-
-  // Helpers for visitSwitch
-  bool handleSmallSwitchRange(CaseRec& CR,
-                              CaseRecVector& WorkList,
-                              Value* SV,
-                              MachineBasicBlock* Default);
-  bool handleJTSwitchCase(CaseRec& CR,
-                          CaseRecVector& WorkList,
-                          Value* SV,
-                          MachineBasicBlock* Default);
-  bool handleBTSplitSwitchCase(CaseRec& CR,
-                               CaseRecVector& WorkList,
-                               Value* SV,
-                               MachineBasicBlock* Default);
-  bool handleBitTestsSwitchCase(CaseRec& CR,
-                                CaseRecVector& WorkList,
-                                Value* SV,
-                                MachineBasicBlock* Default);  
-  void visitSwitchCase(CaseBlock &CB);
-  void visitBitTestHeader(BitTestBlock &B);
-  void visitBitTestCase(MachineBasicBlock* NextMBB,
-                        unsigned Reg,
-                        BitTestCase &B);
-  void visitJumpTable(JumpTable &JT);
-  void visitJumpTableHeader(JumpTable &JT, JumpTableHeader &JTH);
-  
-  // These all get lowered before this pass.
-  void visitInvoke(InvokeInst &I);
-  void visitUnwind(UnwindInst &I);
-
-  void visitBinary(User &I, unsigned OpCode);
-  void visitShift(User &I, unsigned Opcode);
-  void visitAdd(User &I) { 
-    if (I.getType()->isFPOrFPVector())
-      visitBinary(I, ISD::FADD);
-    else
-      visitBinary(I, ISD::ADD);
-  }
-  void visitSub(User &I);
-  void visitMul(User &I) {
-    if (I.getType()->isFPOrFPVector())
-      visitBinary(I, ISD::FMUL);
-    else
-      visitBinary(I, ISD::MUL);
-  }
-  void visitURem(User &I) { visitBinary(I, ISD::UREM); }
-  void visitSRem(User &I) { visitBinary(I, ISD::SREM); }
-  void visitFRem(User &I) { visitBinary(I, ISD::FREM); }
-  void visitUDiv(User &I) { visitBinary(I, ISD::UDIV); }
-  void visitSDiv(User &I) { visitBinary(I, ISD::SDIV); }
-  void visitFDiv(User &I) { visitBinary(I, ISD::FDIV); }
-  void visitAnd (User &I) { visitBinary(I, ISD::AND); }
-  void visitOr  (User &I) { visitBinary(I, ISD::OR); }
-  void visitXor (User &I) { visitBinary(I, ISD::XOR); }
-  void visitShl (User &I) { visitShift(I, ISD::SHL); }
-  void visitLShr(User &I) { visitShift(I, ISD::SRL); }
-  void visitAShr(User &I) { visitShift(I, ISD::SRA); }
-  void visitICmp(User &I);
-  void visitFCmp(User &I);
-  void visitVICmp(User &I);
-  void visitVFCmp(User &I);
-  // Visit the conversion instructions
-  void visitTrunc(User &I);
-  void visitZExt(User &I);
-  void visitSExt(User &I);
-  void visitFPTrunc(User &I);
-  void visitFPExt(User &I);
-  void visitFPToUI(User &I);
-  void visitFPToSI(User &I);
-  void visitUIToFP(User &I);
-  void visitSIToFP(User &I);
-  void visitPtrToInt(User &I);
-  void visitIntToPtr(User &I);
-  void visitBitCast(User &I);
-
-  void visitExtractElement(User &I);
-  void visitInsertElement(User &I);
-  void visitShuffleVector(User &I);
-
-  void visitExtractValue(ExtractValueInst &I);
-  void visitInsertValue(InsertValueInst &I);
-
-  void visitGetElementPtr(User &I);
-  void visitSelect(User &I);
-
-  void visitMalloc(MallocInst &I);
-  void visitFree(FreeInst &I);
-  void visitAlloca(AllocaInst &I);
-  void visitLoad(LoadInst &I);
-  void visitStore(StoreInst &I);
-  void visitPHI(PHINode &I) { } // PHI nodes are handled specially.
-  void visitCall(CallInst &I);
-  void visitInlineAsm(CallSite CS);
-  const char *visitIntrinsicCall(CallInst &I, unsigned Intrinsic);
-  void visitTargetIntrinsic(CallInst &I, unsigned Intrinsic);
-
-  void visitVAStart(CallInst &I);
-  void visitVAArg(VAArgInst &I);
-  void visitVAEnd(CallInst &I);
-  void visitVACopy(CallInst &I);
-
-  void visitUserOp1(Instruction &I) {
-    assert(0 && "UserOp1 should not exist at instruction selection time!");
-    abort();
-  }
-  void visitUserOp2(Instruction &I) {
-    assert(0 && "UserOp2 should not exist at instruction selection time!");
-    abort();
-  }
-  
-private:
-  inline const char *implVisitBinaryAtomic(CallInst& I, ISD::NodeType Op);
-
-};
-} // end namespace llvm
-
-
-/// getCopyFromParts - Create a value that contains the specified legal parts
-/// combined into the value they represent.  If the parts combine to a type
-/// larger then ValueVT then AssertOp can be used to specify whether the extra
-/// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT
-/// (ISD::AssertSext).
-static SDValue getCopyFromParts(SelectionDAG &DAG,
-                                  const SDValue *Parts,
-                                  unsigned NumParts,
-                                  MVT PartVT,
-                                  MVT ValueVT,
-                                  ISD::NodeType AssertOp = ISD::DELETED_NODE) {
-  assert(NumParts > 0 && "No parts to assemble!");
-  TargetLowering &TLI = DAG.getTargetLoweringInfo();
-  SDValue Val = Parts[0];
-
-  if (NumParts > 1) {
-    // Assemble the value from multiple parts.
-    if (!ValueVT.isVector()) {
-      unsigned PartBits = PartVT.getSizeInBits();
-      unsigned ValueBits = ValueVT.getSizeInBits();
-
-      // Assemble the power of 2 part.
-      unsigned RoundParts = NumParts & (NumParts - 1) ?
-        1 << Log2_32(NumParts) : NumParts;
-      unsigned RoundBits = PartBits * RoundParts;
-      MVT RoundVT = RoundBits == ValueBits ?
-        ValueVT : MVT::getIntegerVT(RoundBits);
-      SDValue Lo, Hi;
-
-      if (RoundParts > 2) {
-        MVT HalfVT = MVT::getIntegerVT(RoundBits/2);
-        Lo = getCopyFromParts(DAG, Parts, RoundParts/2, PartVT, HalfVT);
-        Hi = getCopyFromParts(DAG, Parts+RoundParts/2, RoundParts/2,
-                              PartVT, HalfVT);
-      } else {
-        Lo = Parts[0];
-        Hi = Parts[1];
-      }
-      if (TLI.isBigEndian())
-        std::swap(Lo, Hi);
-      Val = DAG.getNode(ISD::BUILD_PAIR, RoundVT, Lo, Hi);
-
-      if (RoundParts < NumParts) {
-        // Assemble the trailing non-power-of-2 part.
-        unsigned OddParts = NumParts - RoundParts;
-        MVT OddVT = MVT::getIntegerVT(OddParts * PartBits);
-        Hi = getCopyFromParts(DAG, Parts+RoundParts, OddParts, PartVT, OddVT);
-
-        // Combine the round and odd parts.
-        Lo = Val;
-        if (TLI.isBigEndian())
-          std::swap(Lo, Hi);