Apply Chris' suggestion.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52970 91177308-0d34-0410-b5e6-96231b3b80d8

1 files changed, 36 insertions, 32 deletions

diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
index 8751c9a086..8ba2b789ec 100644
--- a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
+++ b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
@@ -5303,17 +5303,16 @@ void SelectionDAGISel::ComputeLiveOutVRegInfo(SelectionDAG &DAG) {
 }
 
 void SelectionDAGISel::CodeGenAndEmitDAG(SelectionDAG &DAG) {
-  NamedRegionTimer *RegionTimer = 0;
-
   DOUT << "Lowered selection DAG:\n";
   DEBUG(DAG.dump());
 
   // Run the DAG combiner in pre-legalize mode.
-  if (TimePassesIsEnabled)
-    RegionTimer = new NamedRegionTimer("DAG Combining 1");
-  DAG.Combine(false, *AA);
-  if (TimePassesIsEnabled)
-    delete RegionTimer;
+  if (TimePassesIsEnabled) {
+    NamedRegionTimer T("DAG Combining 1");
+    DAG.Combine(false, *AA);
+  } else {
+    DAG.Combine(false, *AA);
+  }
   
   DOUT << "Optimized lowered selection DAG:\n";
   DEBUG(DAG.dump());
@@ -5324,21 +5323,23 @@ void SelectionDAGISel::CodeGenAndEmitDAG(SelectionDAG &DAG) {
   DAG.LegalizeTypes();
   // Someday even later, enable a dag combine pass here.
 #endif
-  if (TimePassesIsEnabled)
-    RegionTimer = new NamedRegionTimer("DAG Legalization");
-  DAG.Legalize();
-  if (TimePassesIsEnabled)
-    delete RegionTimer;
+  if (TimePassesIsEnabled) {
+    NamedRegionTimer T("DAG Legalization");
+    DAG.Legalize();
+  } else {
+    DAG.Legalize();
+  }
   
   DOUT << "Legalized selection DAG:\n";
   DEBUG(DAG.dump());
   
   // Run the DAG combiner in post-legalize mode.
-  if (TimePassesIsEnabled)
-    RegionTimer = new NamedRegionTimer("DAG Combining 2");
-  DAG.Combine(true, *AA);
-  if (TimePassesIsEnabled)
-    delete RegionTimer;
+  if (TimePassesIsEnabled) {
+    NamedRegionTimer T("DAG Combining 2");
+    DAG.Combine(true, *AA);
+  } else {
+    DAG.Combine(true, *AA);
+  }
   
   DOUT << "Optimized legalized selection DAG:\n";
   DEBUG(DAG.dump());
@@ -5350,26 +5351,29 @@ void SelectionDAGISel::CodeGenAndEmitDAG(SelectionDAG &DAG) {
 
   // Third, instruction select all of the operations to machine code, adding the
   // code to the MachineBasicBlock.
-  if (TimePassesIsEnabled)
-    RegionTimer = new NamedRegionTimer("Instruction Selection");
-  InstructionSelect(DAG);
-  if (TimePassesIsEnabled)
-    delete RegionTimer;
+  if (TimePassesIsEnabled) {
+    NamedRegionTimer T("Instruction Selection");
+    InstructionSelect(DAG);
+  } else {
+    InstructionSelect(DAG);
+  }
 
   // Emit machine code to BB.  This can change 'BB' to the last block being 
   // inserted into.
-  if (TimePassesIsEnabled)
-    RegionTimer = new NamedRegionTimer("Instruction Scheduling");
-  ScheduleAndEmitDAG(DAG);
-  if (TimePassesIsEnabled)
-    delete RegionTimer;
+  if (TimePassesIsEnabled) {
+    NamedRegionTimer T("Instruction Scheduling");
+    ScheduleAndEmitDAG(DAG);
+  } else {
+    ScheduleAndEmitDAG(DAG);
+  }
 
   // Perform target specific isel post processing.
-  if (TimePassesIsEnabled)
-    RegionTimer = new NamedRegionTimer("Instruction Selection Post Processing");
-  InstructionSelectPostProcessing(DAG);
-  if (TimePassesIsEnabled)
-    delete RegionTimer;
+  if (TimePassesIsEnabled) {
+    NamedRegionTimer T("Instruction Selection Post Processing");
+    InstructionSelectPostProcessing(DAG);
+  } else {
+    InstructionSelectPostProcessing(DAG);
+  }
   
   DOUT << "Selected machine code:\n";
   DEBUG(BB->dump());