diff options
author | Chris Lattner <sabre@nondot.org> | 2008-04-28 06:02:19 +0000 |
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committer | Chris Lattner <sabre@nondot.org> | 2008-04-28 06:02:19 +0000 |
commit | 8eaff0449c70a7baa75c6ec5d1d90ea9ac2dad5a (patch) | |
tree | 61ae4b587af67aa6f51e1fd0ec168753094c519e /lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp | |
parent | 5da0b73aa11eca430ed9e03e157f8432870fa50b (diff) |
switch RegsForValue::Regs to be a SmallVector to avoid
heap thrash on tiny (usually single-element) vectors.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50335 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp')
-rw-r--r-- | lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp index d82f0d613a..507b2d731a 100644 --- a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp +++ b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp @@ -125,7 +125,7 @@ namespace { /// Regs - This list holds the register (for legal and promoted values) /// or register set (for expanded values) that the value should be assigned /// to. - std::vector<unsigned> Regs; + SmallVector<unsigned, 4> Regs; /// RegVTs - The value types of the registers. This is the same size /// as ValueVTs; every register contributing to a given value must @@ -146,11 +146,11 @@ namespace { unsigned Reg, MVT::ValueType regvt, MVT::ValueType valuevt) : TLI(&tli), Regs(1, Reg), RegVTs(1, regvt), ValueVTs(1, valuevt) {} RegsForValue(const TargetLowering &tli, - const std::vector<unsigned> ®s, + const SmallVectorImpl<unsigned> ®s, MVT::ValueType regvt, MVT::ValueType valuevt) : TLI(&tli), Regs(regs), RegVTs(1, regvt), ValueVTs(1, valuevt) {} RegsForValue(const TargetLowering &tli, - const std::vector<unsigned> ®s, + const SmallVectorImpl<unsigned> ®s, const SmallVector<MVT::ValueType, 4> ®vts, const SmallVector<MVT::ValueType, 4> &valuevts) : TLI(&tli), Regs(regs), RegVTs(regvts), ValueVTs(valuevts) {} @@ -3600,7 +3600,7 @@ GetRegistersForValue(SDISelAsmOperandInfo &OpInfo, bool HasEarlyClobber, MachineFunction &MF = DAG.getMachineFunction(); - std::vector<unsigned> Regs; + SmallVector<unsigned, 8> Regs; // If this is a constraint for a single physreg, or a constraint for a // register class, find it. |