Fix for PR 1505 (and 1489). Rewrite X87 register

model to include f32 variants.  Some factoring
improvments forthcoming.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37847 91177308-0d34-0410-b5e6-96231b3b80d8

1 files changed, 1 insertions, 9 deletions

diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
index 7a7874b273..4dadde0dfe 100644
--- a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
+++ b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
@@ -3918,15 +3918,7 @@ TargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy,
         Op = DAG.getNode(ExtOp, getTypeToTransformTo(VT), Op);
       } else {
         assert(MVT::isFloatingPoint(VT) && "Not int or FP?");
-        // A true promotion would change the size of the argument.
-        // Instead, pretend this is an int.  If FP objects are not
-        // passed the same as ints, the original type should be Legal
-        // and we should not get here.
-        Op = DAG.getNode(ISD::BIT_CONVERT, 
-                         VT==MVT::f32 ? MVT::i32 :
-                         (VT==MVT::f64 ? MVT::i64 :
-                          MVT::Other),
-                         Op);
+        Op = DAG.getNode(ISD::FP_EXTEND, getTypeToTransformTo(VT), Op);
       }
       Ops.push_back(Op);
       Ops.push_back(DAG.getConstant(Flags, MVT::i32));