Simplify the interface to the schedulers, to not pass the selected heuristicin.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26692 91177308-0d34-0410-b5e6-96231b3b80d8

1 files changed, 15 insertions, 1 deletions

diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
index 26a8717999..fc8e560aaf 100644
--- a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
+++ b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
@@ -57,6 +57,16 @@ static const bool ViewISelDAGs = 0;
 static const bool ViewSchedDAGs = 0;
 #endif
 
+// Scheduling heuristics
+enum SchedHeuristics {
+  defaultScheduling,      // Let the target specify its preference.
+  noScheduling,           // No scheduling, emit breadth first sequence.
+  simpleScheduling,       // Two pass, min. critical path, max. utilization.
+  simpleNoItinScheduling, // Same as above exact using generic latency.
+  listSchedulingBURR,     // Bottom up reg reduction list scheduling.
+  listSchedulingTD        // Top-down list scheduler.
+};
+
 namespace {
   cl::opt<SchedHeuristics>
   ISHeuristic(
@@ -2444,9 +2454,13 @@ void SelectionDAGISel::ScheduleAndEmitDAG(SelectionDAG &DAG) {
       SL = createBURRListDAGScheduler(DAG, BB);
     break;
   case noScheduling:
+    SL = createBFS_DAGScheduler(DAG, BB);
+    break;
   case simpleScheduling:
+    SL = createSimpleDAGScheduler(false, DAG, BB);
+    break;
   case simpleNoItinScheduling:
-    SL = createSimpleDAGScheduler(ISHeuristic, DAG, BB);
+    SL = createSimpleDAGScheduler(true, DAG, BB);
     break;
   case listSchedulingBURR:
     SL = createBURRListDAGScheduler(DAG, BB);