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authorDaniel Dunbar <daniel@zuster.org>2009-05-18 16:43:04 +0000
committerDaniel Dunbar <daniel@zuster.org>2009-05-18 16:43:04 +0000
commit8c562e2d25d319f8bde7a1a60142203f316a2883 (patch)
tree139bda2a4914e0e722a127c7e885836242e93cdf /lib/CodeGen/SelectionDAG/ScheduleDAGSDNodesEmit.cpp
parent10978bd5918689334d44cd30e5cfe06588b6014d (diff)
Silence Release-Asserts warnings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72011 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/CodeGen/SelectionDAG/ScheduleDAGSDNodesEmit.cpp')
-rw-r--r--lib/CodeGen/SelectionDAG/ScheduleDAGSDNodesEmit.cpp4
1 files changed, 4 insertions, 0 deletions
diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodesEmit.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodesEmit.cpp
index f1da2583f3..fb5e207e81 100644
--- a/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodesEmit.cpp
+++ b/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodesEmit.cpp
@@ -119,6 +119,7 @@ void ScheduleDAGSDNodes::EmitCopyFromReg(SDNode *Node, unsigned ResNo,
DstRC, SrcRC);
assert(Emitted && "Unable to issue a copy instruction!\n");
+ (void) Emitted;
}
SDValue Op(Node, ResNo);
@@ -254,6 +255,7 @@ ScheduleDAGSDNodes::AddRegisterOperand(MachineInstr *MI, SDValue Op,
bool Emitted = TII->copyRegToReg(*BB, InsertPos, NewVReg, VReg,
DstRC, SrcRC);
assert(Emitted && "Unable to issue a copy instruction!\n");
+ (void) Emitted;
VReg = NewVReg;
}
}
@@ -445,6 +447,7 @@ ScheduleDAGSDNodes::EmitCopyToRegClassNode(SDNode *Node,
DstRC, SrcRC);
assert(Emitted &&
"Unable to issue a copy instruction for a COPY_TO_REGCLASS node!\n");
+ (void) Emitted;
SDValue Op(Node, 0);
bool isNew = VRBaseMap.insert(std::make_pair(Op, NewVReg)).second;
@@ -568,6 +571,7 @@ void ScheduleDAGSDNodes::EmitNode(SDNode *Node, bool IsClone, bool IsCloned,
bool Emitted = TII->copyRegToReg(*BB, InsertPos, DestReg, SrcReg,
DstTRC, SrcTRC);
assert(Emitted && "Unable to issue a copy instruction!\n");
+ (void) Emitted;
break;
}
case ISD::CopyFromReg: {