diff options
| author | Andrew Trick <atrick@apple.com> | 2011-06-15 17:16:12 +0000 |
|---|---|---|
| committer | Andrew Trick <atrick@apple.com> | 2011-06-15 17:16:12 +0000 |
| commit | 4cb971ce1c8b254f29365c988b55f6dcfe86d21e (patch) | |
| tree | 0a968ce5996f0908c5464ac1742d279c9c29ff3a /lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp | |
| parent | 0e7f08bde50164de545007d9fbd1ab887434bd8a (diff) | |
Added -stress-sched flag in the Asserts build.
Added a test case for handling physreg aliases during pre-RA-sched.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133063 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp')
| -rw-r--r-- | lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp index 9f2f0121a8..0d656efb37 100644 --- a/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp +++ b/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp @@ -435,7 +435,7 @@ void ScheduleDAGSDNodes::AddSchedEdges() { // it requires a cross class copy (cost < 0). That means we are only // treating "expensive to copy" register dependency as physical register // dependency. This may change in the future though. - if (Cost >= 0) + if (Cost >= 0 && !StressSched) PhysReg = 0; // If this is a ctrl dep, latency is 1. |