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| author | Evan Cheng <evan.cheng@apple.com> | 2010-10-28 01:49:06 +0000 |
|---|---|---|
| committer | Evan Cheng <evan.cheng@apple.com> | 2010-10-28 01:49:06 +0000 |
| commit | 0104d9de04f5620ad9f837efbd3d82f31c6ff451 (patch) | |
| tree | 47a891a2ed427ede38018df7b39f4015b85511f5 /lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp | |
| parent | 7c88cdcc3ba49101fa119ec3b403e9980934384e (diff) | |
- Assign load / store with shifter op address modes the right itinerary classes.
- For now, loads of [r, r] addressing mode is the same as the
[r, r lsl/lsr/asr #] variants. ARMBaseInstrInfo::getOperandLatency() should
identify the former case and reduce the output latency by 1.
- Also identify [r, r << 2] case. This special form of shifter addressing mode
is "free".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117519 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp')
0 files changed, 0 insertions, 0 deletions