Initial support for carrying MachineInstrs in SUnits.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59278 91177308-0d34-0410-b5e6-96231b3b80d8

1 files changed, 10 insertions, 0 deletions

diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAGEmit.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAGEmit.cpp
index 2c40d97a7e..d60dd49357 100644
--- a/lib/CodeGen/SelectionDAG/ScheduleDAGEmit.cpp
+++ b/lib/CodeGen/SelectionDAG/ScheduleDAGEmit.cpp
@@ -684,6 +684,16 @@ MachineBasicBlock *ScheduleDAG::EmitSchedule() {
       EmitNoop();
       continue;
     }
+
+    // For post-regalloc scheduling, we already have the instruction;
+    // just append it to the block.
+    if (!DAG) {
+      BB->push_back(SU->getInstr());
+      continue;
+    }
+
+    // For pre-regalloc scheduling, create instructions corresponding to the
+    // SDNode and any flagged SDNodes and append them to the block.
     SmallVector<SDNode *, 4> FlaggedNodes;
     for (SDNode *N = SU->getNode()->getFlaggedNode(); N; N = N->getFlaggedNode())
       FlaggedNodes.push_back(N);