diff options
| author | Dale Johannesen <dalej@apple.com> | 2008-09-12 17:49:03 +0000 |
|---|---|---|
| committer | Dale Johannesen <dalej@apple.com> | 2008-09-12 17:49:03 +0000 |
| commit | 913d3dfac43f29921467f33aa743f28ee1bfc5d1 (patch) | |
| tree | c8d41ba2614bd1798f9553e689f4489fbc1ee330 /lib/CodeGen/SelectionDAG/ScheduleDAGEmit.cpp | |
| parent | f5aeb1a8e4cf272c7348376d185ef8d8267653e0 (diff) | |
Pass "earlyclobber" bit through to machine
representation; coalescer and RA need to know
about it. No functional change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56161 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/CodeGen/SelectionDAG/ScheduleDAGEmit.cpp')
| -rw-r--r-- | lib/CodeGen/SelectionDAG/ScheduleDAGEmit.cpp | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAGEmit.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAGEmit.cpp index 52b2cf40d0..ffe5c5c82f 100644 --- a/lib/CodeGen/SelectionDAG/ScheduleDAGEmit.cpp +++ b/lib/CodeGen/SelectionDAG/ScheduleDAGEmit.cpp @@ -592,6 +592,13 @@ void ScheduleDAG::EmitNode(SDNode *Node, bool IsClone, MI->addOperand(MachineOperand::CreateReg(Reg, true)); } break; + case 6: // Def of earlyclobber register. + for (; NumVals; --NumVals, ++i) { + unsigned Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg(); + MI->addOperand(MachineOperand::CreateReg(Reg, true, false, false, + false, 0, true)); + } + break; case 1: // Use of register. case 3: // Immediate. case 4: // Addressing mode. |