Fix PR611, codegen'ing SREM of FP operands to fmod or fmodf instead of

the sequence used for integer ops


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22629 91177308-0d34-0410-b5e6-96231b3b80d8

1 files changed, 12 insertions, 6 deletions

diff --git a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
index 9e9f4fa487..69cd725caf 100644
--- a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
+++ b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
@@ -1306,12 +1306,18 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
     case TargetLowering::Promote:
     case TargetLowering::Custom:
       assert(0 && "Cannot promote/custom handle this yet!");
-    case TargetLowering::Expand: {
-      MVT::ValueType VT = Node->getValueType(0);
-      unsigned Opc = (Node->getOpcode() == ISD::UREM) ? ISD::UDIV : ISD::SDIV;
-      Result = DAG.getNode(Opc, VT, Tmp1, Tmp2);
-      Result = DAG.getNode(ISD::MUL, VT, Result, Tmp2);
-      Result = DAG.getNode(ISD::SUB, VT, Tmp1, Result);
+    case TargetLowering::Expand:
+      if (MVT::isInteger(Node->getValueType(0))) {
+        MVT::ValueType VT = Node->getValueType(0);
+        unsigned Opc = (Node->getOpcode() == ISD::UREM) ? ISD::UDIV : ISD::SDIV;
+        Result = DAG.getNode(Opc, VT, Tmp1, Tmp2);
+        Result = DAG.getNode(ISD::MUL, VT, Result, Tmp2);
+        Result = DAG.getNode(ISD::SUB, VT, Tmp1, Result);
+      } else {
+        // Floating point mod -> fmod libcall.
+        const char *FnName = Node->getValueType(0) == MVT::f32 ? "fmodf":"fmod";
+        SDOperand Dummy;
+        Result = ExpandLibCall(FnName, Node, Dummy);
       }
       break;
     }