diff options
author | Dan Gohman <gohman@apple.com> | 2010-07-02 00:10:16 +0000 |
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committer | Dan Gohman <gohman@apple.com> | 2010-07-02 00:10:16 +0000 |
commit | 89496d0eb73ab8771b27b3d9c1db6492d8eefc3a (patch) | |
tree | 6a793eda3720fd43af1f9a5515e0271abd5090c9 /lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp | |
parent | f12ad66741afc9bfc313f20cf34edef8e4133c18 (diff) |
Rename CreateReg to CreateRegs, and MakeReg to CreateReg.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107451 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp')
-rw-r--r-- | lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp | 9 |
1 files changed, 5 insertions, 4 deletions
diff --git a/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp b/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp index c9712ef367..78599fdb49 100644 --- a/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp +++ b/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp @@ -172,18 +172,19 @@ void FunctionLoweringInfo::clear() { ArgDbgValues.clear(); } -unsigned FunctionLoweringInfo::MakeReg(EVT VT) { +/// CreateReg - Allocate a single virtual register for the given type. +unsigned FunctionLoweringInfo::CreateReg(EVT VT) { return RegInfo->createVirtualRegister(TLI.getRegClassFor(VT)); } -/// CreateReg - Allocate the appropriate number of virtual registers of +/// CreateRegs - Allocate the appropriate number of virtual registers of /// the correctly promoted or expanded types. Assign these registers /// consecutive vreg numbers and return the first assigned number. /// /// In the case that the given value has struct or array type, this function /// will assign registers for each member or element. /// -unsigned FunctionLoweringInfo::CreateReg(const Type *Ty) { +unsigned FunctionLoweringInfo::CreateRegs(const Type *Ty) { SmallVector<EVT, 4> ValueVTs; ComputeValueVTs(TLI, Ty, ValueVTs); @@ -194,7 +195,7 @@ unsigned FunctionLoweringInfo::CreateReg(const Type *Ty) { unsigned NumRegs = TLI.getNumRegisters(Ty->getContext(), ValueVT); for (unsigned i = 0; i != NumRegs; ++i) { - unsigned R = MakeReg(RegisterVT); + unsigned R = CreateReg(RegisterVT); if (!FirstReg) FirstReg = R; } } |