diff options
| author | Dan Gohman <gohman@apple.com> | 2008-10-03 15:45:36 +0000 |
|---|---|---|
| committer | Dan Gohman <gohman@apple.com> | 2008-10-03 15:45:36 +0000 |
| commit | d735b8019b0f297d7c14b55adcd887af24d8e602 (patch) | |
| tree | 9019ef6d07a30709c5afbe52903a7cdfd9615cb1 /lib/CodeGen/RegAllocSimple.cpp | |
| parent | 06a62886fbca6214945958e28b16a82b470f6b2e (diff) | |
Switch the MachineOperand accessors back to the short names like
isReg, etc., from isRegister, etc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57006 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/CodeGen/RegAllocSimple.cpp')
| -rw-r--r-- | lib/CodeGen/RegAllocSimple.cpp | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/lib/CodeGen/RegAllocSimple.cpp b/lib/CodeGen/RegAllocSimple.cpp index 87b09a2a0d..da729ae8df 100644 --- a/lib/CodeGen/RegAllocSimple.cpp +++ b/lib/CodeGen/RegAllocSimple.cpp @@ -190,7 +190,7 @@ void RegAllocSimple::AllocateBasicBlock(MachineBasicBlock &MBB) { for (int i = MI->getNumOperands() - 1; i >= 0; --i) { MachineOperand &MO = MI->getOperand(i); - if (MO.isRegister() && MO.getReg() && + if (MO.isReg() && MO.getReg() && TargetRegisterInfo::isVirtualRegister(MO.getReg())) { unsigned virtualReg = (unsigned) MO.getReg(); DOUT << "op: " << MO << "\n"; @@ -209,7 +209,7 @@ void RegAllocSimple::AllocateBasicBlock(MachineBasicBlock &MBB) { // must be same register number as the source operand that is // tied to. This maps a = b + c into b = b + c, and saves b into // a's spot. - assert(MI->getOperand(TiedOp).isRegister() && + assert(MI->getOperand(TiedOp).isReg() && MI->getOperand(TiedOp).getReg() && MI->getOperand(TiedOp).isUse() && "Two address instruction invalid!"); |