diff options
author | Alkis Evlogimenos <alkis@evlogimenos.com> | 2004-07-21 12:00:10 +0000 |
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committer | Alkis Evlogimenos <alkis@evlogimenos.com> | 2004-07-21 12:00:10 +0000 |
commit | fc29e63afec1e8f4636c13bd9723b27efc2d4c73 (patch) | |
tree | 51a717a485dca3aac3ffe7401a098653fff65831 /lib/CodeGen/RegAllocIterativeScan.cpp | |
parent | 2d54705c4b8c83b47cb7d03d488b3eda34158ada (diff) |
Clear spilled list at once. Remove unused vector.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15073 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/CodeGen/RegAllocIterativeScan.cpp')
-rw-r--r-- | lib/CodeGen/RegAllocIterativeScan.cpp | 5 |
1 files changed, 2 insertions, 3 deletions
diff --git a/lib/CodeGen/RegAllocIterativeScan.cpp b/lib/CodeGen/RegAllocIterativeScan.cpp index 63fd358451..3f380aaf9d 100644 --- a/lib/CodeGen/RegAllocIterativeScan.cpp +++ b/lib/CodeGen/RegAllocIterativeScan.cpp @@ -161,14 +161,14 @@ bool RA::runOnMachineFunction(MachineFunction &fn) { // the spill code and restart the algorithm std::set<unsigned> spilledRegs; for (IntervalPtrs::iterator - i = spilled_.begin(); i != spilled_.end(); ) { + i = spilled_.begin(); i != spilled_.end(); ++i) { int slot = vrm_->assignVirt2StackSlot((*i)->reg); std::vector<LiveInterval*> added = li_->addIntervalsForSpills(**i, *vrm_, slot); std::copy(added.begin(), added.end(), std::back_inserter(handled_)); spilledRegs.insert((*i)->reg); - i = spilled_.erase(i); } + spilled_.clear(); for (IntervalPtrs::iterator i = handled_.begin(); i != handled_.end(); ) if (spilledRegs.count((*i)->reg)) @@ -415,7 +415,6 @@ void RA::assignRegOrSpillAtInterval(IntervalPtrs::value_type cur) // otherwise we spill all intervals aliasing the register with // minimum weight, assigned the newly cleared register to the // current interval and continue - std::vector<LiveInterval*> added; assert(MRegisterInfo::isPhysicalRegister(minReg) && "did not choose a register to spill?"); std::vector<bool> toSpill(mri_->getNumRegs(), false); |