diff options
author | Chris Lattner <sabre@nondot.org> | 2005-09-19 06:56:21 +0000 |
---|---|---|
committer | Chris Lattner <sabre@nondot.org> | 2005-09-19 06:56:21 +0000 |
commit | cea8688ee4637e0f3cffc75e47f15be756f043bf (patch) | |
tree | 1b0e41edebe492610040333cd7d060e16536e2ea /lib/CodeGen/RegAllocIterativeScan.cpp | |
parent | a92aab74dd303c81537169cb53935665199c3afc (diff) |
Teach the local spiller to turn stack slot loads into register-register copies
when possible, avoiding the load (and avoiding the copy if the value is already
in the right register).
This patch came about when I noticed code like the following being generated:
store R17 -> [SS1]
...blah...
R4 = load [SS1]
This was causing an LSU reject on the G5. This problem was due to the register
allocator folding spill code into a reg-reg copy (producing the load), which
prevented the spiller from being able to rewrite the load into a copy, despite
the fact that the value was already available in a register. In the case
above, we now rip out the R4 load and replace it with a R4 = R17 copy.
This speeds up several programs on X86 (which spills a lot :) ), e.g.
smg2k from 22.39->20.60s, povray from 12.93->12.66s, 168.wupwise from
68.54->53.83s (!), 197.parser from 7.33->6.62s (!), etc. This may have a larger
impact in some cases on the G5 (by avoiding LSU rejects), though it probably
won't trigger as often (less spilling in general).
Targets that implement folding of loads/stores into copies should implement
the isLoadFromStackSlot hook to get this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23388 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/CodeGen/RegAllocIterativeScan.cpp')
0 files changed, 0 insertions, 0 deletions