Rename the redundant MachineOperand::getOperandType() to MachineOperand::getType()

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4331 91177308-0d34-0410-b5e6-96231b3b80d8

2 files changed, 17 insertions, 17 deletions

diff --git a/lib/CodeGen/RegAlloc/LiveRangeInfo.cpp b/lib/CodeGen/RegAlloc/LiveRangeInfo.cpp
index 31bd134e1b..76f559401f 100644
--- a/lib/CodeGen/RegAlloc/LiveRangeInfo.cpp
+++ b/lib/CodeGen/RegAlloc/LiveRangeInfo.cpp
@@ -110,7 +110,7 @@ LiveRangeInfo::createOrAddToLiveRange(const Value* Def, bool isCC /* = false*/)
 
   // check if the LR is already there (because of multiple defs)
   if (!DefRange) { 
-    DefRange = this->createNewLiveRange(Def, isCC);
+    DefRange = createNewLiveRange(Def, isCC);
   } else {                          // live range already exists
     DefRange->insert(Def);          // add the operand to the range
     LiveRangeMap[Def] = DefRange;   // make operand point to merged set
@@ -134,7 +134,7 @@ void LiveRangeInfo::constructLiveRanges() {
   // first find the live ranges for all incoming args of the function since
   // those LRs start from the start of the function
   for (Function::const_aiterator AI = Meth->abegin(); AI != Meth->aend(); ++AI)
-    this->createNewLiveRange(AI, /*isCC*/ false);
+    createNewLiveRange(AI, /*isCC*/ false);
 
   // Now suggest hardware registers for these function args 
   MRI.suggestRegs4MethodArgs(Meth, *this);
@@ -160,7 +160,7 @@ void LiveRangeInfo::constructLiveRanges() {
       // 
       if(TM.getInstrInfo().isReturn(MInst->getOpCode()) ||
 	 TM.getInstrInfo().isCall(MInst->getOpCode()))
-	CallRetInstrList.push_back( MInst ); 
+	CallRetInstrList.push_back(MInst); 
  
       // iterate over explicit MI operands and create a new LR
       // for each operand that is defined by the instruction
@@ -168,9 +168,9 @@ void LiveRangeInfo::constructLiveRanges() {
              OpE = MInst->end(); OpI != OpE; ++OpI)
 	if (OpI.isDef()) {     
 	  const Value *Def = *OpI;
-          bool isCC = (OpI.getMachineOperand().getOperandType()
+          bool isCC = (OpI.getMachineOperand().getType()
                        == MachineOperand::MO_CCRegister);
-          this->createOrAddToLiveRange(Def, isCC);
+          createOrAddToLiveRange(Def, isCC);
 	}
 
       // iterate over implicit MI operands and create a new LR
@@ -178,7 +178,7 @@ void LiveRangeInfo::constructLiveRanges() {
       for (unsigned i = 0; i < MInst->getNumImplicitRefs(); ++i) 
 	if (MInst->implicitRefIsDefined(i)) {     
 	  const Value *Def = MInst->getImplicitRef(i);
-          this->createOrAddToLiveRange(Def, /*isCC*/ false);
+          createOrAddToLiveRange(Def, /*isCC*/ false);
 	}
 
     } // for all machine instructions in the BB
diff --git a/lib/CodeGen/RegAlloc/PhyRegAlloc.cpp b/lib/CodeGen/RegAlloc/PhyRegAlloc.cpp
index 4dcd44f458..9660e9f607 100644
--- a/lib/CodeGen/RegAlloc/PhyRegAlloc.cpp
+++ b/lib/CodeGen/RegAlloc/PhyRegAlloc.cpp
@@ -539,8 +539,8 @@ void PhyRegAlloc::updateMachineCode()
       for (unsigned OpNum=0; OpNum < MInst->getNumOperands(); ++OpNum)
         {
           MachineOperand& Op = MInst->getOperand(OpNum);
-          if (Op.getOperandType() ==  MachineOperand::MO_VirtualRegister || 
-              Op.getOperandType() ==  MachineOperand::MO_CCRegister)
+          if (Op.getType() ==  MachineOperand::MO_VirtualRegister || 
+              Op.getType() ==  MachineOperand::MO_CCRegister)
             {
               const Value *const Val =  Op.getVRegValue();
           
@@ -750,7 +750,7 @@ int PhyRegAlloc::getUsableUniRegAtMI(const int RegType,
                                      std::vector<MachineInstr*>& MIBef,
                                      std::vector<MachineInstr*>& MIAft) {
   
-  RegClass* RC = this->getRegClassByID(MRI.getRegClassIDOfRegType(RegType));
+  RegClass* RC = getRegClassByID(MRI.getRegClassIDOfRegType(RegType));
   
   int RegU =  getUnusedUniRegAtMI(RC, MInst, LVSetBef);
   
@@ -766,8 +766,8 @@ int PhyRegAlloc::getUsableUniRegAtMI(const int RegType,
     int scratchRegType = -1;
     if (MRI.regTypeNeedsScratchReg(RegType, scratchRegType))
       {
-        int scratchReg = this->getUsableUniRegAtMI(scratchRegType, LVSetBef,
-                                                   MInst, MIBef, MIAft);
+        int scratchReg = getUsableUniRegAtMI(scratchRegType, LVSetBef,
+                                             MInst, MIBef, MIAft);
         assert(scratchReg != MRI.getInvalidRegNum());
         
         // We may as well hold the value in the scratch register instead
@@ -893,8 +893,8 @@ void PhyRegAlloc::setRelRegsUsedByThisInst(RegClass *RC,
     {
       const MachineOperand& Op = MInst->getOperand(OpNum);
       
-      if (Op.getOperandType() == MachineOperand::MO_VirtualRegister || 
-          Op.getOperandType() == MachineOperand::MO_CCRegister)
+      if (MInst->getOperandType(OpNum) == MachineOperand::MO_VirtualRegister || 
+          MInst->getOperandType(OpNum) == MachineOperand::MO_CCRegister)
         if (const Value* Val = Op.getVRegValue())
           if (MRI.getRegClassIDOfValue(Val) == RC->getID())
             if (Op.getAllocatedRegNum() == -1)
@@ -971,9 +971,9 @@ void PhyRegAlloc::printMachineCode()
       for (unsigned OpNum=0; OpNum < MInst->getNumOperands(); ++OpNum) {
 	MachineOperand& Op = MInst->getOperand(OpNum);
 
-	if (Op.getOperandType() ==  MachineOperand::MO_VirtualRegister || 
-	    Op.getOperandType() ==  MachineOperand::MO_CCRegister /*|| 
-	    Op.getOperandType() ==  MachineOperand::MO_PCRelativeDisp*/ ) {
+	if (Op.getType() ==  MachineOperand::MO_VirtualRegister || 
+	    Op.getType() ==  MachineOperand::MO_CCRegister /*|| 
+	    Op.getType() ==  MachineOperand::MO_PCRelativeDisp*/ ) {
 
 	  const Value *const Val = Op.getVRegValue () ;
 	  // ****this code is temporary till NULL Values are fixed
@@ -1005,7 +1005,7 @@ void PhyRegAlloc::printMachineCode()
 	  }
 
 	} 
-	else if (Op.getOperandType() ==  MachineOperand::MO_MachineRegister) {
+	else if (Op.getType() ==  MachineOperand::MO_MachineRegister) {
 	  cerr << "\t" << "%" << MRI.getUnifiedRegName(Op.getMachineRegNum());
 	}