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| author | Misha Brukman <brukman+llvm@gmail.com> | 2003-05-31 06:25:19 +0000 |
|---|---|---|
| committer | Misha Brukman <brukman+llvm@gmail.com> | 2003-05-31 06:25:19 +0000 |
| commit | 33cc12319c02c4be933222f2ed5145d3c80718fd (patch) | |
| tree | 6aee095e423a7042e74f174881c4970202259d25 /lib/CodeGen/RegAlloc/PhyRegAlloc.cpp | |
| parent | 286903909f0c7293b5e6001c78f965a627348711 (diff) | |
The 'rd' register is consistently mentioned last in instruction definitions.
Created new classes from which instructions inherit their ordering of fields.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6461 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/CodeGen/RegAlloc/PhyRegAlloc.cpp')
0 files changed, 0 insertions, 0 deletions