diff options
| author | Chris Lattner <sabre@nondot.org> | 2009-07-29 21:36:49 +0000 |
|---|---|---|
| committer | Chris Lattner <sabre@nondot.org> | 2009-07-29 21:36:49 +0000 |
| commit | 2a3868849438a0a0ad4f9a50f2b94eb1639b554e (patch) | |
| tree | 207c400577ae0d0da9afc4e32ae7c7eaabd04318 /lib/CodeGen/PostRASchedulerList.cpp | |
| parent | 20a2a0aff3221e2c777558d714753bae0f296c8d (diff) | |
inline the global 'getInstrOperandRegClass' function into its callers
now that TargetOperandInfo does the heavy lifting.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77508 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/CodeGen/PostRASchedulerList.cpp')
| -rw-r--r-- | lib/CodeGen/PostRASchedulerList.cpp | 11 |
1 files changed, 7 insertions, 4 deletions
diff --git a/lib/CodeGen/PostRASchedulerList.cpp b/lib/CodeGen/PostRASchedulerList.cpp index c02647a130..b90a6dde9c 100644 --- a/lib/CodeGen/PostRASchedulerList.cpp +++ b/lib/CodeGen/PostRASchedulerList.cpp @@ -449,8 +449,10 @@ void SchedulePostRATDList::PrescanInstruction(MachineInstr *MI) { if (!MO.isReg()) continue; unsigned Reg = MO.getReg(); if (Reg == 0) continue; - const TargetRegisterClass *NewRC = - getInstrOperandRegClass(TRI, MI->getDesc(), i); + const TargetRegisterClass *NewRC = 0; + + if (i < MI->getDesc().getNumOperands()) + NewRC = MI->getDesc().OpInfo[i].getRegClass(TRI); // For now, only allow the register to be changed if its register // class is consistent across all uses. @@ -521,8 +523,9 @@ void SchedulePostRATDList::ScanInstruction(MachineInstr *MI, if (Reg == 0) continue; if (!MO.isUse()) continue; - const TargetRegisterClass *NewRC = - getInstrOperandRegClass(TRI, MI->getDesc(), i); + const TargetRegisterClass *NewRC = 0; + if (i < MI->getDesc().getNumOperands()) + NewRC = MI->getDesc().OpInfo[i].getRegClass(TRI); // For now, only allow the register to be changed if its register // class is consistent across all uses. |