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| author | Vikram S. Adve <vadve@cs.uiuc.edu> | 2003-05-27 00:07:13 +0000 |
|---|---|---|
| committer | Vikram S. Adve <vadve@cs.uiuc.edu> | 2003-05-27 00:07:13 +0000 |
| commit | bfebd79dd11a04974ea71f79a160c31fc45a91af (patch) | |
| tree | 497cc3d2e1a5e1edaac78f3d9ef3be8947dd8687 /lib/CodeGen/ModuloScheduling | |
| parent | a22eace55bb17af2728ca494b6d4557bdad82a09 (diff) | |
(1) Added special register class containing (for now) %fsr.
Fixed spilling of %fcc[0-3] which are part of %fsr.
(2) Moved some machine-independent reg-class code to class TargetRegInfo
from SparcReg{Class,}Info.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6343 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/CodeGen/ModuloScheduling')
0 files changed, 0 insertions, 0 deletions