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authorSilviu Baranga <silviu.baranga@arm.com>2012-03-20 15:54:56 +0000
committerSilviu Baranga <silviu.baranga@arm.com>2012-03-20 15:54:56 +0000
commit5c062ad92672f22e61a4b20a9954af3db3b72bd6 (patch)
treef65d4278663391396a3ae5ab55a3a4b7021200ed /lib/CodeGen/MachineSink.cpp
parent8da7a4668f6f32e565d426b5cca93eea9278f482 (diff)
The ARM instructions that have an unpredictable behavior when the pc register operand is given now fail with soft fail. Modified the regression tests to reflect this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153089 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/CodeGen/MachineSink.cpp')
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