Initial support for register pressure aware scheduling. The register reduction

scheduler can go into a "vertical mode" (i.e. traversing up the two-address
chain, etc.) when the register pressure is low.
This does seem to reduce the number of spills in the cases I've looked at. But
with x86, it's no guarantee the performance of the code improves.
It can be turned on with -sched-vertically option.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28108 91177308-0d34-0410-b5e6-96231b3b80d8

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