diff options
author | Evan Cheng <evan.cheng@apple.com> | 2009-08-05 01:29:24 +0000 |
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committer | Evan Cheng <evan.cheng@apple.com> | 2009-08-05 01:29:24 +0000 |
commit | 518ad1a88031cd4a667bb2e54688fce7dc2ae133 (patch) | |
tree | daed2c0cf274e185855e6a58074c881f1114fbc8 /lib/CodeGen/LowerSubregs.cpp | |
parent | a5225add0d748bd6396f3e4e77669a8996d9ecec (diff) |
If the insert_subreg source is <undef>, insert an implicit_def instead of a copy.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78141 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/CodeGen/LowerSubregs.cpp')
-rw-r--r-- | lib/CodeGen/LowerSubregs.cpp | 10 |
1 files changed, 8 insertions, 2 deletions
diff --git a/lib/CodeGen/LowerSubregs.cpp b/lib/CodeGen/LowerSubregs.cpp index 9c23a5ac15..e9e60a00f0 100644 --- a/lib/CodeGen/LowerSubregs.cpp +++ b/lib/CodeGen/LowerSubregs.cpp @@ -254,7 +254,13 @@ bool LowerSubregsInstructionPass::LowerInsert(MachineInstr *MI) { // Insert sub-register copy const TargetRegisterClass *TRC0= TRI.getPhysicalRegisterRegClass(DstSubReg); const TargetRegisterClass *TRC1= TRI.getPhysicalRegisterRegClass(InsReg); - TII.copyRegToReg(*MBB, MI, DstSubReg, InsReg, TRC0, TRC1); + if (MI->getOperand(2).isUndef()) + // If the source register being inserted is undef, then this becomes an + // implicit_def. + BuildMI(*MBB, MI, MI->getDebugLoc(), + TII.get(TargetInstrInfo::IMPLICIT_DEF), DstSubReg); + else + TII.copyRegToReg(*MBB, MI, DstSubReg, InsReg, TRC0, TRC1); MachineBasicBlock::iterator CopyMI = MI; --CopyMI; @@ -270,7 +276,7 @@ bool LowerSubregsInstructionPass::LowerInsert(MachineInstr *MI) { } // Make sure the inserted register gets killed - if (MI->getOperand(2).isKill()) + if (MI->getOperand(2).isKill() && !MI->getOperand(2).isUndef()) TransferKillFlag(MI, InsReg, TRI); } |