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| author | Jakob Stoklund Olesen <stoklund@2pi.dk> | 2011-06-15 23:28:14 +0000 |
|---|---|---|
| committer | Jakob Stoklund Olesen <stoklund@2pi.dk> | 2011-06-15 23:28:14 +0000 |
| commit | f28987b76e758b5f2fcc2c5d2c8e073df54ca91e (patch) | |
| tree | 8f60dc5b88bbfc1192d2a780d9a5ee6702535e5f /lib/CodeGen/LLVMTargetMachine.cpp | |
| parent | f14bacc862eb69c7c779858746cc020386ce5590 (diff) | |
Use set operations instead of plain lists to enumerate register classes.
This simplifies many of the target description files since it is common
for register classes to be related or contain sequences of numbered
registers.
I have verified that this doesn't change the files generated by TableGen
for ARM and X86. It alters the allocation order of MBlaze GPR and Mips
FGR32 registers, but I believe the change is benign.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133105 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/CodeGen/LLVMTargetMachine.cpp')
0 files changed, 0 insertions, 0 deletions