diff options
| author | Jim Grosbach <grosbach@apple.com> | 2012-04-05 23:51:24 +0000 |
|---|---|---|
| committer | Jim Grosbach <grosbach@apple.com> | 2012-04-05 23:51:24 +0000 |
| commit | 3ef737608ab005f320c2e20fcb3b914c677616ed (patch) | |
| tree | c7124d51eba70af247dfadb55beb0384f8accfd9 /lib/CodeGen/InterferenceCache.cpp | |
| parent | 42730cec0b6b19986bf83db2490f70de8c8139fa (diff) | |
ARM: Don't form a t2LDRi8 or t2STRi8 with an offset of zero.
The load/store optimizer splits LDRD/STRD into two instructions when the
register pairing doesn't work out. For negative offsets in Thumb2, it uses
t2STRi8 to do that. That's fine, except for the case when the offset is in
the range [-4,-1]. In that case, we'll also form a second t2STRi8 with
the original offset plus 4, resulting in a t2STRi8 with a non-negative
offset, which ends up as if it were an STRT, which is completely bogus.
Similarly for loads.
No testcase, unfortunately, as any I've been able to construct is both large
and extremely fragile.
rdar://11193937
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154141 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/CodeGen/InterferenceCache.cpp')
0 files changed, 0 insertions, 0 deletions