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| author | Owen Anderson <resistor@mac.com> | 2011-06-16 18:17:13 +0000 |
|---|---|---|
| committer | Owen Anderson <resistor@mac.com> | 2011-06-16 18:17:13 +0000 |
| commit | 1300f3019e5d590231bbc3d907626708515d3212 (patch) | |
| tree | 8841668d876a6bf2ddff54374637595982e87969 /lib/Analysis/BranchProbabilityInfo.cpp | |
| parent | 43641a5d17e525f339d6cf51010a42a9479dc2a5 (diff) | |
Change the REG_SEQUENCE SDNode to take an explict register class ID as its first operand. This operand is lowered away by the time we reach MachineInstrs, so the actual register-allocation handling of them doesn't need to change.
This is intended to support using REG_SEQUENCE SDNode's with type MVT::untyped, and is part of the long road to eliminating some of the hacks we currently use to support register pairs and other strange constraints, particularly on ARM NEON.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133178 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Analysis/BranchProbabilityInfo.cpp')
0 files changed, 0 insertions, 0 deletions