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| author | Jakob Stoklund Olesen <stoklund@2pi.dk> | 2012-01-24 18:06:05 +0000 |
|---|---|---|
| committer | Jakob Stoklund Olesen <stoklund@2pi.dk> | 2012-01-24 18:06:05 +0000 |
| commit | 5b52f6d655e34de5c6fedbb71b6c94775cc10032 (patch) | |
| tree | 147d3d1569f63029f88d6f987730ba84081f31f3 /include | |
| parent | 9136f2112ca67bf360ee64b6546abea9dce0579c (diff) | |
Add an (interleave A, B, ...) SetTheory operator.
This will interleave the elements from two or more lists.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148824 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'include')
| -rw-r--r-- | include/llvm/Target/Target.td | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/include/llvm/Target/Target.td b/include/llvm/Target/Target.td index f9f30a8bb7..84e6b1bfef 100644 --- a/include/llvm/Target/Target.td +++ b/include/llvm/Target/Target.td @@ -200,12 +200,15 @@ class RegisterClass<string namespace, list<ValueType> regTypes, int alignment, // // (decimate GPR, 2) - Pick every N'th element, starting with the first. // +// (interleave A, B, ...) - Interleave the elements from each argument list. +// // All of these operators work on ordered sets, not lists. That means // duplicates are removed from sub-expressions. // Set operators. The rest is defined in TargetSelectionDAG.td. def sequence; def decimate; +def interleave; // RegisterTuples - Automatically generate super-registers by forming tuples of // sub-registers. This is useful for modeling register sequence constraints |