diff options
author | Eli Friedman <eli.friedman@gmail.com> | 2009-07-24 07:43:59 +0000 |
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committer | Eli Friedman <eli.friedman@gmail.com> | 2009-07-24 07:43:59 +0000 |
commit | 23ed52752bb40a9085c9d36bbc6603972c3e0080 (patch) | |
tree | 20e0ea1df0d0ad6dcb38ed0cf471061324cc5052 /include | |
parent | 050578fb4a006d7a183662f83fc22f7c78475605 (diff) |
Remove unused member functions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76960 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'include')
-rw-r--r-- | include/llvm/Target/TargetInstrInfo.h | 22 |
1 files changed, 0 insertions, 22 deletions
diff --git a/include/llvm/Target/TargetInstrInfo.h b/include/llvm/Target/TargetInstrInfo.h index 538d1390a1..5e1a9cf9d4 100644 --- a/include/llvm/Target/TargetInstrInfo.h +++ b/include/llvm/Target/TargetInstrInfo.h @@ -284,18 +284,6 @@ public: assert(0 && "Target didn't implement TargetInstrInfo::storeRegToStackSlot!"); } - /// storeRegToAddr - Store the specified register of the given register class - /// to the specified address. The store instruction is to be added to the - /// given machine basic block before the specified machine instruction. If - /// isKill is true, the register operand is the last use and must be marked - /// kill. - virtual void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill, - SmallVectorImpl<MachineOperand> &Addr, - const TargetRegisterClass *RC, - SmallVectorImpl<MachineInstr*> &NewMIs) const { - assert(0 && "Target didn't implement TargetInstrInfo::storeRegToAddr!"); - } - /// loadRegFromStackSlot - Load the specified register of the given register /// class from the specified stack frame index. The load instruction is to be /// added to the given machine basic block before the specified machine @@ -306,16 +294,6 @@ public: const TargetRegisterClass *RC) const { assert(0 && "Target didn't implement TargetInstrInfo::loadRegFromStackSlot!"); } - - /// loadRegFromAddr - Load the specified register of the given register class - /// class from the specified address. The load instruction is to be added to - /// the given machine basic block before the specified machine instruction. - virtual void loadRegFromAddr(MachineFunction &MF, unsigned DestReg, - SmallVectorImpl<MachineOperand> &Addr, - const TargetRegisterClass *RC, - SmallVectorImpl<MachineInstr*> &NewMIs) const { - assert(0 && "Target didn't implement TargetInstrInfo::loadRegFromAddr!"); - } /// spillCalleeSavedRegisters - Issues instruction(s) to spill all callee /// saved registers and returns true if it isn't possible / profitable to do |