A lot of formatting changes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68431 91177308-0d34-0410-b5e6-96231b3b80d8

1 files changed, 1470 insertions, 1105 deletions

diff --git a/docs/WritingAnLLVMBackend.html b/docs/WritingAnLLVMBackend.html
index 08da132028..a1dc34c75b 100644
--- a/docs/WritingAnLLVMBackend.html
+++ b/docs/WritingAnLLVMBackend.html
@@ -54,7 +54,8 @@
 </ol>
 
 <div class="doc_author">    
-  <p>Written by <a href="http://www.woo.com">Mason Woo</a> and <a href="http://misha.brukman.net">Misha Brukman</a></p>
+  <p>Written by <a href="http://www.woo.com">Mason Woo</a> and
+                <a href="http://misha.brukman.net">Misha Brukman</a></p>
 </div>
 
 <!-- *********************************************************************** -->
@@ -64,23 +65,30 @@
 <!-- *********************************************************************** -->
 
 <div class="doc_text">
-<p>This document describes techniques for writing compiler backends
-that convert the LLVM IR (intermediate representation) to code for a specified
-machine or other languages. Code intended for a specific machine can take the
-form of either assembly code or binary code (usable for a JIT compiler). </p>
-
-<p>The backend of LLVM features a target-independent code generator
-that may create output for several types of target CPUs, including X86,
-PowerPC, Alpha, and SPARC. The backend may also be used to generate code
-targeted at SPUs of the Cell processor or GPUs to support the execution of
-compute kernels.</p>
-
-<p>The document focuses on existing examples found in subdirectories
-of <tt>llvm/lib/Target</tt> in a downloaded LLVM release. In particular, this document
-focuses on the example of creating a static compiler (one that emits text
-assembly) for a SPARC target, because SPARC has fairly standard
+
+<p>
+This document describes techniques for writing compiler backends that convert
+the LLVM Intermediate Representation (IR) to code for a specified machine or
+other languages. Code intended for a specific machine can take the form of
+either assembly code or binary code (usable for a JIT compiler).
+</p>
+
+<p>
+The backend of LLVM features a target-independent code generator that may create
+output for several types of target CPUs &mdash; including X86, PowerPC, Alpha,
+and SPARC. The backend may also be used to generate code targeted at SPUs of the
+Cell processor or GPUs to support the execution of compute kernels.
+</p>
+
+<p>
+The document focuses on existing examples found in subdirectories
+of <tt>llvm/lib/Target</tt> in a downloaded LLVM release. In particular, this
+document focuses on the example of creating a static compiler (one that emits
+text assembly) for a SPARC target, because SPARC has fairly standard
 characteristics, such as a RISC instruction set and straightforward calling
-conventions.</p>
+conventions.
+</p>
+
 </div>
 
 <div class="doc_subsection">
@@ -88,8 +96,12 @@ conventions.</p>
 </div>  
 
 <div class="doc_text">
-<p>The audience for this document is anyone who needs to write an
-LLVM backend to generate code for a specific hardware or software target.</p>  
+
+<p>
+The audience for this document is anyone who needs to write an LLVM backend to
+generate code for a specific hardware or software target.
+</p>
+
 </div>
 
 <div class="doc_subsection">
@@ -97,149 +109,174 @@ LLVM backend to generate code for a specific hardware or software target.</p>
 </div>  
 
 <div class="doc_text">  
-These essential documents must be read before reading this document:  
+
+<p>
+These essential documents must be read before reading this document:
+</p>
+
 <ul>
-<li>
-<i><a href="http://www.llvm.org/docs/LangRef.html">LLVM Language Reference Manual</a></i> - 
-a reference manual for the LLVM assembly language
-</li>
-<li>
-<i><a href="http://www.llvm.org/docs/CodeGenerator.html">The LLVM Target-Independent Code Generator </a></i> - 
-a guide to the components (classes and code generation algorithms) for translating 
-the LLVM internal representation to the machine code for a specified target. 
-Pay particular attention to the descriptions of code generation stages: 
-Instruction Selection, Scheduling and Formation, SSA-based Optimization, 
-Register Allocation, Prolog/Epilog Code Insertion, Late Machine Code Optimizations, 
-and Code Emission. 
-</li>
-<li>
-<i><a href="http://www.llvm.org/docs/TableGenFundamentals.html">TableGen Fundamentals</a></i> - 
-a document that describes the TableGen (tblgen) application that manages domain-specific 
-information to support LLVM code generation. TableGen processes input from a 
-target description file (.td suffix) and generates C++ code that can be used 
-for code generation.
-</li>
-<li>
-<i><a href="http://www.llvm.org/docs/WritingAnLLVMPass.html">Writing an LLVM Pass</a></i> - 
-The assembly printer is a FunctionPass, as are several SelectionDAG processing steps.
-</li>
+<li><i><a href="http://www.llvm.org/docs/LangRef.html">LLVM Language Reference
+    Manual</a></i> &mdash; a reference manual for the LLVM assembly language.</li>
+
+<li><i><a href="http://www.llvm.org/docs/CodeGenerator.html">The LLVM
+    Target-Independent Code Generator</a></i> &mdash; a guide to the components
+    (classes and code generation algorithms) for translating the LLVM internal
+    representation into machine code for a specified target.  Pay particular
+    attention to the descriptions of code generation stages: Instruction
+    Selection, Scheduling and Formation, SSA-based Optimization, Register
+    Allocation, Prolog/Epilog Code Insertion, Late Machine Code Optimizations,
+    and Code Emission.</li>
+
+<li><i><a href="http://www.llvm.org/docs/TableGenFundamentals.html">TableGen
+    Fundamentals</a></i> &mdash;a document that describes the TableGen
+    (<tt>tblgen</tt>) application that manages domain-specific information to
+    support LLVM code generation. TableGen processes input from a target
+    description file (<tt>.td</tt> suffix) and generates C++ code that can be
+    used for code generation.</li>
+
+<li><i><a href="http://www.llvm.org/docs/WritingAnLLVMPass.html">Writing an LLVM
+    Pass</a></i> &mdash; The assembly printer is a <tt>FunctionPass</tt>, as are
+    several SelectionDAG processing steps.</li>
 </ul>
-To follow the SPARC examples in this document, have a copy of 
-<i><a href="http://www.sparc.org/standards/V8.pdf">The SPARC Architecture Manual, Version 8</a></i> 
-for reference. For details about the ARM instruction set, refer to the 
-<i><a href="http://infocenter.arm.com/">ARM Architecture Reference Manual</a></i>
-For more about the GNU Assembler format (GAS), see 
-<i><a href="http://sourceware.org/binutils/docs/as/index.html">Using As</a></i>
-especially for the assembly printer. <i>Using As</i> contains lists of target machine dependent features. 
+
+<p>
+To follow the SPARC examples in this document, have a copy of
+<i><a href="http://www.sparc.org/standards/V8.pdf">The SPARC Architecture
+Manual, Version 8</a></i> for reference. For details about the ARM instruction
+set, refer to the <i><a href="http://infocenter.arm.com/">ARM Architecture
+Reference Manual</a></i>. For more about the GNU Assembler format
+(<tt>GAS</tt>), see
+<i><a href="http://sourceware.org/binutils/docs/as/index.html">Using As</a></i>,
+especially for the assembly printer. <i>Using As</i> contains a list of target
+machine dependent features.
+</p>
+
 </div>
 
 <div class="doc_subsection">
   <a name="Basic">Basic Steps</a>
 </div>
+
 <div class="doc_text">
-<p>To write a compiler
-backend for LLVM that converts the LLVM IR (intermediate representation)
-to code for a specified target (machine or other language), follow these steps:</p>
+
+<p>
+To write a compiler backend for LLVM that converts the LLVM IR to code for a
+specified target (machine or other language), follow these steps:
+</p>
 
 <ul>
-<li>
-Create a subclass of the TargetMachine class that describes
-characteristics of your target machine. Copy existing examples of specific
-TargetMachine class and header files; for example, start with <tt>SparcTargetMachine.cpp</tt>
-and <tt>SparcTargetMachine.h</tt>, but change the file names for your target. Similarly,
-change code that references &quot;Sparc&quot; to reference your target. </li>
-
-<li>Describe the register set of the target. Use TableGen to generate
-code for register definition, register aliases, and register classes from a
-target-specific <tt>RegisterInfo.td</tt> input file. You should also write additional
-code for a subclass of TargetRegisterInfo class that represents the class
-register file data used for register allocation and also describes the
-interactions between registers.</li>
-
-<li>Describe the instruction set of the target. Use TableGen to
-generate code for target-specific instructions from target-specific versions of
-<tt>TargetInstrFormats.td</tt> and <tt>TargetInstrInfo.td</tt>. You should write additional code
-for a subclass of the TargetInstrInfo
-class to represent machine
-instructions supported by the target machine. </li>
-
-<li>Describe the selection and conversion of the LLVM IR from a DAG (directed
-acyclic graph) representation of instructions to native target-specific
-instructions. Use TableGen to generate code that matches patterns and selects
-instructions based on additional information in a target-specific version of
-<tt>TargetInstrInfo.td</tt>. Write code for <tt>XXXISelDAGToDAG.cpp</tt> 
-(where XXX identifies the specific target) to perform pattern
-matching and DAG-to-DAG instruction selection. Also write code in <tt>XXXISelLowering.cpp</tt>
-to replace or remove operations and data types that are not supported natively
-in a SelectionDAG. </li>
-
-<li>Write code for an
-assembly printer that converts LLVM IR to a GAS format for your target machine.
-You should add assembly strings to the instructions defined in your
-target-specific version of <tt>TargetInstrInfo.td</tt>. You should also write code for a
-subclass of AsmPrinter that performs the LLVM-to-assembly conversion and a
-trivial subclass of TargetAsmInfo.</li>
-
-<li>Optionally, add support for subtargets (that is, variants with
-different capabilities). You should also write code for a subclass of the
-TargetSubtarget class, which allows you to use the <tt>-mcpu=</tt> 
-and <tt>-mattr=</tt> command-line options.</li>
-
-<li>Optionally, add JIT support and create a machine code emitter (subclass
-of TargetJITInfo) that is used to emit binary code directly into memory. </li>
+<li>Create a subclass of the TargetMachine class that describes characteristics
+    of your target machine. Copy existing examples of specific TargetMachine
+    class and header files; for example, start with
+    <tt>SparcTargetMachine.cpp</tt> and <tt>SparcTargetMachine.h</tt>, but
+    change the file names for your target. Similarly, change code that
+    references "Sparc" to reference your target. </li>
+
+<li>Describe the register set of the target. Use TableGen to generate code for
+    register definition, register aliases, and register classes from a
+    target-specific <tt>RegisterInfo.td</tt> input file. You should also write
+    additional code for a subclass of the TargetRegisterInfo class that
+    represents the class register file data used for register allocation and
+    also describes the interactions between registers.</li>
+
+<li>Describe the instruction set of the target. Use TableGen to generate code
+    for target-specific instructions from target-specific versions of
+    <tt>TargetInstrFormats.td</tt> and <tt>TargetInstrInfo.td</tt>. You should
+    write additional code for a subclass of the TargetInstrInfo class to
+    represent machine instructions supported by the target machine. </li>
+
+<li>Describe the selection and conversion of the LLVM IR from a Directed Acyclic
+    Graph (DAG) representation of instructions to native target-specific
+    instructions. Use TableGen to generate code that matches patterns and
+    selects instructions based on additional information in a target-specific
+    version of <tt>TargetInstrInfo.td</tt>. Write code
+    for <tt>XXXISelDAGToDAG.cpp</tt>, where XXX identifies the specific target,
+    to perform pattern matching and DAG-to-DAG instruction selection. Also write
+    code in <tt>XXXISelLowering.cpp</tt> to replace or remove operations and
+    data types that are not supported natively in a SelectionDAG. </li>
+
+<li>Write code for an assembly printer that converts LLVM IR to a GAS format for
+    your target machine.  You should add assembly strings to the instructions
+    defined in your target-specific version of <tt>TargetInstrInfo.td</tt>. You
+    should also write code for a subclass of AsmPrinter that performs the
+    LLVM-to-assembly conversion and a trivial subclass of TargetAsmInfo.</li>
+
+<li>Optionally, add support for subtargets (i.e., variants with different
+    capabilities). You should also write code for a subclass of the
+    TargetSubtarget class, which allows you to use the <tt>-mcpu=</tt>
+    and <tt>-mattr=</tt> command-line options.</li>
+
+<li>Optionally, add JIT support and create a machine code emitter (subclass of
+    TargetJITInfo) that is used to emit binary code directly into memory. </li>
 </ul>
 
-<p>In the .cpp and .h files, initially stub up these methods and
+<p>
+In the <tt>.cpp</tt> and <tt>.h</tt>. files, initially stub up these methods and
 then implement them later. Initially, you may not know which private members
-that the class will need and which components will need to be subclassed.</p>
+that the class will need and which components will need to be subclassed.
+</p>
+
 </div>
 
 <div class="doc_subsection">
   <a name="Preliminaries">Preliminaries</a>
 </div>
+
 <div class="doc_text">
-<p>To actually create
-your compiler backend, you need to create and modify a few files. The absolute
-minimum is discussed here, but to actually use the LLVM target-independent code
-generator, you must perform the steps described in the <a
-href="http://www.llvm.org/docs/CodeGenerator.html">LLVM
-Target-Independent Code Generator</a> document.</p>
-
-<p>First, you should
-create a subdirectory under <tt>lib/Target</tt> to hold all the files related to your
-target. If your target is called &quot;Dummy&quot;, create the directory
-<tt>lib/Target/Dummy</tt>.</p>
-
-<p>In this new
-directory, create a <tt>Makefile</tt>. It is easiest to copy a <tt>Makefile</tt> of another
-target and modify it. It should at least contain the <tt>LEVEL</tt>, <tt>LIBRARYNAME</tt> and
-<tt>TARGET</tt> variables, and then include <tt>$(LEVEL)/Makefile.common</tt>. The library can be
-named LLVMDummy (for example, see the MIPS target). Alternatively, you can
-split the library into LLVMDummyCodeGen and LLVMDummyAsmPrinter, the latter of
-which should be implemented in a subdirectory below <tt>lib/Target/Dummy</tt> (for
-example, see the PowerPC target).</p>
-
-<p>Note that these two
-naming schemes are hardcoded into <tt>llvm-config</tt>. Using any other naming scheme
-will confuse <tt>llvm-config</tt> and produce lots of (seemingly unrelated) linker
-errors when linking <tt>llc</tt>.</p>
-
-<p>To make your target
-actually do something, you need to implement a subclass of TargetMachine. This
-implementation should typically be in the file
-<tt>lib/Target/DummyTargetMachine.cpp</tt>, but any file in the <tt>lib/Target</tt> directory will
-be built and should work. To use LLVM's target
-independent code generator, you should do what all current machine backends do: create a subclass
-of LLVMTargetMachine. (To create a target from scratch, create a subclass of
-TargetMachine.)</p>
-
-<p>To get LLVM to
-actually build and link your target, you need to add it to the <tt>TARGETS_TO_BUILD</tt>
-variable. To do this, you modify the configure script to know about your target
-when parsing the <tt>--enable-targets</tt> option. Search the configure script for <tt>TARGETS_TO_BUILD</tt>,
-add your target to the lists there (some creativity required) and then
+
+<p>
+To actually create your compiler backend, you need to create and modify a few
+files. The absolute minimum is discussed here. But to actually use the LLVM
+target-independent code generator, you must perform the steps described in
+the <a href="http://www.llvm.org/docs/CodeGenerator.html">LLVM
+Target-Independent Code Generator</a> document.
+</p>
+
+<p>
+First, you should create a subdirectory under <tt>lib/Target</tt> to hold all
+the files related to your target. If your target is called "Dummy," create the
+directory <tt>lib/Target/Dummy</tt>.
+</p>
+
+<p>
+In this new
+directory, create a <tt>Makefile</tt>. It is easiest to copy a
+<tt>Makefile</tt> of another target and modify it. It should at least contain
+the <tt>LEVEL</tt>, <tt>LIBRARYNAME</tt> and <tt>TARGET</tt> variables, and then
+include <tt>$(LEVEL)/Makefile.common</tt>. The library can be
+named <tt>LLVMDummy</tt> (for example, see the MIPS target). Alternatively, you
+can split the library into <tt>LLVMDummyCodeGen</tt>
+and <tt>LLVMDummyAsmPrinter</tt>, the latter of which should be implemented in a
+subdirectory below <tt>lib/Target/Dummy</tt> (for example, see the PowerPC
+target).
+</p>
+
+<p>
+Note that these two naming schemes are hardcoded into <tt>llvm-config</tt>.
+Using any other naming scheme will confuse <tt>llvm-config</tt> and produce a
+lot of (seemingly unrelated) linker errors when linking <tt>llc</tt>.
+</p>
+
+<p>
+To make your target actually do something, you need to implement a subclass of
+<tt>TargetMachine</tt>. This implementation should typically be in the file
+<tt>lib/Target/DummyTargetMachine.cpp</tt>, but any file in
+the <tt>lib/Target</tt> directory will be built and should work. To use LLVM's
+target independent code generator, you should do what all current machine
+backends do: create a subclass of <tt>LLVMTargetMachine</tt>. (To create a
+target from scratch, create a subclass of <tt>TargetMachine</tt>.)
+</p>
+
+<p>
+To get LLVM to actually build and link your target, you need to add it to
+the <tt>TARGETS_TO_BUILD</tt> variable. To do this, you modify the configure
+script to know about your target when parsing the <tt>--enable-targets</tt>
+option. Search the configure script for <tt>TARGETS_TO_BUILD</tt>, add your
+target to the lists there (some creativity required), and then
 reconfigure. Alternatively, you can change <tt>autotools/configure.ac</tt> and
-regenerate configure by running <tt>./autoconf/AutoRegen.sh</tt></p>
+regenerate configure by running <tt>./autoconf/AutoRegen.sh</tt>.
+</p>
+
 </div>
 
 <!-- *********************************************************************** -->
@@ -247,36 +284,47 @@ regenerate configure by running <tt>./autoconf/AutoRegen.sh</tt></p>
   <a name="TargetMachine">Target Machine</a>
 </div>
 <!-- *********************************************************************** -->
+
 <div class="doc_text">
-<p>LLVMTargetMachine is designed as a base class for targets
-implemented with the LLVM target-independent code generator. The
-LLVMTargetMachine class should be specialized by a concrete target class that
-implements the various virtual methods. LLVMTargetMachine is defined as a
-subclass of TargetMachine in <tt>include/llvm/Target/TargetMachine.h</tt>. The
-TargetMachine class implementation (<tt>TargetMachine.cpp</tt>) also processes numerous
-command-line options.  </p>
-
-<p>To create a concrete target-specific subclass of
-LLVMTargetMachine, start by copying an existing TargetMachine class and header.
-You should name the files that you create to reflect your specific target. For
+
+<p>
+<tt>LLVMTargetMachine</tt> is designed as a base class for targets implemented
+with the LLVM target-independent code generator. The <tt>LLVMTargetMachine</tt>
+class should be specialized by a concrete target class that implements the
+various virtual methods. <tt>LLVMTargetMachine</tt> is defined as a subclass of
+<tt>TargetMachine</tt> in <tt>include/llvm/Target/TargetMachine.h</tt>. The
+<tt>TargetMachine</tt> class implementation (<tt>TargetMachine.cpp</tt>) also
+processes numerous command-line options.
+</p>
+
+<p>
+To create a concrete target-specific subclass of <tt>LLVMTargetMachine</tt>,
+start by copying an existing <tt>TargetMachine</tt> class and header.  You
+should name the files that you create to reflect your specific target. For
 instance, for the SPARC target, name the files <tt>SparcTargetMachine.h</tt> and
-<tt>SparcTargetMachine.cpp</tt></p>
+<tt>SparcTargetMachine.cpp</tt>.
+</p>
 
-<p>For a target machine XXX, the implementation of XXXTargetMachine
-must have access methods to obtain objects that represent target components.
-These methods are named <tt>get*Info</tt> and are intended to obtain the instruction set
-(<tt>getInstrInfo</tt>), register set (<tt>getRegisterInfo</tt>), stack frame layout
-(<tt>getFrameInfo</tt>), and similar information. XXXTargetMachine must also implement
-the <tt>getTargetData</tt> method to access an object with target-specific data
-characteristics, such as data type size and alignment requirements. </p>
+<p>
+For a target machine <tt>XXX</tt>, the implementation of
+<tt>XXXTargetMachine</tt> must have access methods to obtain objects that
+represent target components.  These methods are named <tt>get*Info</tt>, and are
+intended to obtain the instruction set (<tt>getInstrInfo</tt>), register set
+(<tt>getRegisterInfo</tt>), stack frame layout (<tt>getFrameInfo</tt>), and
+similar information. <tt>XXXTargetMachine</tt> must also implement the
+<tt>getTargetData</tt> method to access an object with target-specific data
+characteristics, such as data type size and alignment requirements.
+</p>
 
-<p>For instance, for the SPARC target, the header file <tt>SparcTargetMachine.h</tt>
-declares prototypes for several <tt>get*Info</tt> and <tt>getTargetData</tt> methods that simply
-return a class member.  </p>
-</div>
+<p>
+For instance, for the SPARC target, the header file
+<tt>SparcTargetMachine.h</tt> declares prototypes for several <tt>get*Info</tt>
+and <tt>getTargetData</tt> methods that simply return a class member.
+</p>
 
 <div class="doc_code">
-<pre>namespace llvm {
+<pre>
+namespace llvm {
 
 class Module;
 
@@ -287,8 +335,7 @@ class SparcTargetMachine : public LLVMTargetMachine {
   TargetFrameInfo FrameInfo;
   
 protected:
-  virtual const TargetAsmInfo *createTargetAsmInfo()
-const;
+  virtual const TargetAsmInfo *createTargetAsmInfo() const;
   
 public:
   SparcTargetMachine(const Module &amp;M, const std::string &amp;FS);
@@ -313,110 +360,141 @@ public:
 </pre>
 </div>
 
+</div>
+
+
 <div class="doc_text">
+
 <ul>
-<li><tt>getInstrInfo </tt></li>
-<li><tt>getRegisterInfo</tt></li>
-<li><tt>getFrameInfo</tt></li>
-<li><tt>getTargetData</tt></li>
-<li><tt>getSubtargetImpl</tt></li>
+<li><tt>getInstrInfo()</tt></li>
+<li><tt>getRegisterInfo()</tt></li>
+<li><tt>getFrameInfo()</tt></li>
+<li><tt>getTargetData()</tt></li>
+<li><tt>getSubtargetImpl()</tt></li>
 </ul>
-<p>For some targets, you also need to support the following methods:
-</p>
+
+<p>For some targets, you also need to support the following methods:</p>
 
 <ul>
-<li><tt>getTargetLowering </tt></li>
-<li><tt>getJITInfo</tt></li>
+<li><tt>getTargetLowering()</tt></li>
+<li><tt>getJITInfo()</tt></li>
 </ul>
-<p>In addition, the XXXTargetMachine constructor should specify a
-TargetDescription string that determines the data layout for the target machine,
-including characteristics such as pointer size, alignment, and endianness. For
-example, the constructor for SparcTargetMachine contains the following: </p>
-</div>
+
+<p>
+In addition, the <tt>XXXTargetMachine</tt> constructor should specify a
+<tt>TargetDescription</tt> string that determines the data layout for the target
+machine, including characteristics such as pointer size, alignment, and
+endianness. For example, the constructor for SparcTargetMachine contains the
+following:
+</p>
 
 <div class="doc_code">
 <pre>
 SparcTargetMachine::SparcTargetMachine(const Module &amp;M, const std::string &amp;FS)
-  : DataLayout(&quot;E-p:32:32-f128:128:128&quot;),
+  : DataLayout("E-p:32:32-f128:128:128"),
     Subtarget(M, FS), InstrInfo(Subtarget),
     FrameInfo(TargetFrameInfo::StackGrowsDown, 8, 0) {
 }
 </pre>
 </div>
 
+</div>
+
 <div class="doc_text">
-<p>Hyphens separate portions of the TargetDescription string. </p>
+
+<p>Hyphens separate portions of the <tt>TargetDescription</tt> string.</p>
+
 <ul>
-<li>The &quot;E&quot; in the string indicates a big-endian target data model; a
-lower-case &quot;e&quot; would indicate little-endian. </li>
-<li>&quot;p:&quot; is followed by pointer information: size, ABI alignment, and
-preferred alignment. If only two figures follow &quot;p:&quot;, then the first value is
-pointer size, and the second value is both ABI and preferred alignment.</li>
-<li>then a letter for numeric type alignment: &quot;i&quot;, &quot;f&quot;, &quot;v&quot;, or &quot;a&quot;
-(corresponding to integer, floating point, vector, or aggregate). &quot;i&quot;, &quot;v&quot;, or
-&quot;a&quot; are followed by ABI alignment and preferred alignment. &quot;f&quot; is followed by
-three values, the first indicates the size of a long double, then ABI alignment
-and preferred alignment.</li>
+<li>An upper-case "<tt>E</tt>" in the string indicates a big-endian target data
+    model. a lower-case "<tt>e</tt>" indicates little-endian.</li>
+
+<li>"<tt>p:</tt>" is followed by pointer information: size, ABI alignment, and
+    preferred alignment. If only two figures follow "<tt>p:</tt>", then the
+    first value is pointer size, and the second value is both ABI and preferred
+    alignment.</li>
+
+<li>Then a letter for numeric type alignment: "<tt>i</tt>", "<tt>f</tt>",
+    "<tt>v</tt>", or "<tt>a</tt>" (corresponding to integer, floating point,
+    vector, or aggregate). "<tt>i</tt>", "<tt>v</tt>", or "<tt>a</tt>" are
+    followed by ABI alignment and preferred alignment. "<tt>f</tt>" is followed
+    by three values: the first indicates the size of a long double, then ABI
+    alignment, and then ABI preferred alignment.</li>
 </ul>
-<p>You must also register your target using the RegisterTarget
-template. (See the TargetMachineRegistry class.) For example, in <tt>SparcTargetMachine.cpp</tt>,
-the target is registered with:</p>
-</div>
+
+<p>
+You must also register your target using the <tt>RegisterTarget</tt>
+template. (See the <tt>TargetMachineRegistry</tt> class.) For example,
+in <tt>SparcTargetMachine.cpp</tt>, the target is registered with:
+</p>
 
 <div class="doc_code">
 <pre>
 namespace {
   // Register the target.
-  RegisterTarget&lt;SparcTargetMachine&gt;X(&quot;sparc&quot;, &quot;SPARC&quot;);
+  RegisterTarget&lt;SparcTargetMachine&gt;X("sparc", "SPARC");
 }
 </pre>
 </div>
 
+</div>
+
 <!-- *********************************************************************** -->
 <div class="doc_section">
   <a name="RegisterSet">Register Set and Register Classes</a>
 </div>
 <!-- *********************************************************************** -->
+
 <div class="doc_text">
-<p>You should describe
-a concrete target-specific class
-that represents the register file of a target machine. This class is
-called XXXRegisterInfo (where XXX identifies the target) and represents the
-class register file data that is used for register allocation and also
-describes the interactions between registers. </p>
-
-<p>You also need to
-define register classes to categorize related registers. A register class
-should be added for groups of registers that are all treated the same way for
-some instruction. Typical examples are register classes that include integer,
-floating-point, or vector registers. A&nbsp;register allocator allows an
+
+<p>
+You should describe a concrete target-specific class that represents the
+register file of a target machine. This class is called <tt>XXXRegisterInfo</tt>
+(where <tt>XXX</tt> identifies the target) and represents the class register
+file data that is used for register allocation. It also describes the
+interactions between registers.
+</p>
+
+<p>
+You also need to define register classes to categorize related registers. A
+register class should be added for groups of registers that are all treated the
+same way for some instruction. Typical examples are register classes for
+integer, floating-point, or vector registers. A register allocator allows an
 instruction to use any register in a specified register class to perform the
 instruction in a similar manner. Register classes allocate virtual registers to
 instructions from these sets, and register classes let the target-independent
-register allocator automatically choose the actual registers.</p>
+register allocator automatically choose the actual registers.
+</p>
+
+<p>
+Much of the code for registers, including register definition, register aliases,
+and register classes, is generated by TableGen from <tt>XXXRegisterInfo.td</tt>
+input files and placed in <tt>XXXGenRegisterInfo.h.inc</tt> and
+<tt>XXXGenRegisterInfo.inc</tt> output files. Some of the code in the
+implementation of <tt>XXXRegisterInfo</tt> requires hand-coding.
+</p>
 
-<p>Much of the code for registers, including register definition,
-register aliases, and register classes, is generated by TableGen from
-<tt>XXXRegisterInfo.td</tt> input files and placed in <tt>XXXGenRegisterInfo.h.inc</tt> and
-<tt>XXXGenRegisterInfo.inc</tt> output files. Some of the code in the implementation of
-XXXRegisterInfo requires hand-coding. </p>
 </div>
 
 <!-- ======================================================================= -->
 <div class="doc_subsection">
   <a name="RegisterDef">Defining a Register</a>
 </div>
+
 <div class="doc_text">
-<p>The <tt>XXXRegisterInfo.td</tt> file typically starts with register definitions
-for a target machine. The Register class (specified in <tt>Target.td</tt>) is used to
-define an object for each register. The specified string n becomes the Name of
-the register. The basic Register object does not have any subregisters and does
-not specify any aliases.</p>
-</div>
+
+<p>
+The <tt>XXXRegisterInfo.td</tt> file typically starts with register definitions
+for a target machine. The <tt>Register</tt> class (specified
+in <tt>Target.td</tt>) is used to define an object for each register. The
+specified string <tt>n</tt> becomes the <tt>Name</tt> of the register. The
+basic <tt>Register</tt> object does not have any subregisters and does not
+specify any aliases.
+</p>
+
 <div class="doc_code">
 <pre>
 class Register&lt;string n&gt; {
-  string Namespace = &quot;&quot;;
+  string Namespace = "";
   string AsmName = n;
   string Name = n;
   int SpillSize = 0;
@@ -428,47 +506,51 @@ class Register&lt;string n&gt; {
 </pre>
 </div>
 
-<div class="doc_text">
-<p>For example, in the <tt>X86RegisterInfo.td</tt> file, there are register
-definitions that utilize the Register class, such as:</p>
-</div>
+<p>
+For example, in the <tt>X86RegisterInfo.td</tt> file, there are register
+definitions that utilize the Register class, such as:
+</p>
+
 <div class="doc_code">
 <pre>
-def AL : Register&lt;&quot;AL&quot;&gt;,
-DwarfRegNum&lt;[0, 0, 0]&gt;;
+def AL : Register&lt;"AL"&gt;, DwarfRegNum&lt;[0, 0, 0]&gt;;
 </pre>
 </div>
 
-<div class="doc_text">
-<p>This defines the register AL and assigns it values (with
-DwarfRegNum) that are used by <tt>gcc</tt>, <tt>gdb</tt>, or a debug information writer (such as
-DwarfWriter in <tt>llvm/lib/CodeGen</tt>) to identify a register. For register AL,
-DwarfRegNum takes an array of 3 values, representing 3 different modes: the
-first element is for X86-64, the second for EH (exception handling) on X86-32,
-and the third is generic. -1 is a special Dwarf number that indicates the gcc
-number is undefined, and -2 indicates the register number is invalid for this
-mode.</p>
-
-<p>From the previously described line in the <tt>X86RegisterInfo.td</tt>
-file, TableGen generates this code in the <tt>X86GenRegisterInfo.inc</tt> file:</p>
-</div>
+<p>
+This defines the register <tt>AL</tt> and assigns it values (with
+<tt>DwarfRegNum</tt>) that are used by <tt>gcc</tt>, <tt>gdb</tt>, or a debug
+information writer (such as <tt>DwarfWriter</tt>
+in <tt>llvm/lib/CodeGen/AsmPrinter</tt>) to identify a register. For register
+<tt>AL</tt>, <tt>DwarfRegNum</tt> takes an array of 3 values representing 3
+different modes: the first element is for X86-64, the second for exception
+handling (EH) on X86-32, and the third is generic. -1 is a special Dwarf number
+that indicates the gcc number is undefined, and -2 indicates the register number
+is invalid for this mode.
+</p>
+
+<p>
+From the previously described line in the <tt>X86RegisterInfo.td</tt> file,
+TableGen generates this code in the <tt>X86GenRegisterInfo.inc</tt> file:
+</p>
+
 <div class="doc_code">
 <pre>
-  static const unsigned GR8[] = { X86::AL, ... };
-&nbsp;
-  const unsigned AL_AliasSet[] = { X86::AX, X86::EAX, X86::RAX, 0 };
-&nbsp;
-  const TargetRegisterDesc RegisterDescriptors[] = { 
-    ...
-    { &quot;AL&quot;, &quot;AL&quot;, AL_AliasSet, Empty_SubRegsSet, Empty_SubRegsSet, AL_SuperRegsSet }, ...
+static const unsigned GR8[] = { X86::AL, ... };
+
+const unsigned AL_AliasSet[] = { X86::AX, X86::EAX, X86::RAX, 0 };
+
+const TargetRegisterDesc RegisterDescriptors[] = { 
+  ...
+{ "AL", "AL", AL_AliasSet, Empty_SubRegsSet, Empty_SubRegsSet, AL_SuperRegsSet }, ...
 </pre>
 </div>
 
-<div class="doc_text">
-<p>From the register info file, TableGen generates a
-TargetRegisterDesc object for each register. TargetRegisterDesc is defined in
-<tt>include/llvm/Target/TargetRegisterInfo.h</tt> with the following fields:</p>
-</div>
+<p>
+From the register info file, TableGen generates a <tt>TargetRegisterDesc</tt>
+object for each register. <tt>TargetRegisterDesc</tt> is defined in
+<tt>include/llvm/Target/TargetRegisterInfo.h</tt> with the following fields:
+</p>
 
 <div class="doc_code">
 <pre>
@@ -482,41 +564,47 @@ struct TargetRegisterDesc {
 };</pre>
 </div>
 
-<div class="doc_text">
-<p>TableGen uses the entire target description file (<tt>.td</tt>) to
-determine text names for the register (in the AsmName and Name fields of
-TargetRegisterDesc) and the relationships of other registers to the defined
-register (in the other TargetRegisterDesc fields). In this example, other
-definitions establish the registers &quot;AX&quot;, &quot;EAX&quot;, and &quot;RAX&quot; as aliases for one
-another, so TableGen generates a null-terminated array (AL_AliasSet) for this
-register alias set. </p>
-
-<p>The Register class is commonly used as a base class for more
-complex classes. In <tt>Target.td</tt>, the Register class is the base for the
-RegisterWithSubRegs class that is used to define registers that need to specify
-subregisters in the SubRegs list, as shown here:</p>
-</div>
+<p>
+TableGen uses the entire target description file (<tt>.td</tt>) to determine
+text names for the register (in the <tt>AsmName</tt> and <tt>Name</tt> fields of
+<tt>TargetRegisterDesc</tt>) and the relationships of other registers to the
+defined register (in the other <tt>TargetRegisterDesc</tt> fields). In this
+example, other definitions establish the registers "<tt>AX</tt>",
+"<tt>EAX</tt>", and "<tt>RAX</tt>" as aliases for one another, so TableGen
+generates a null-terminated array (<tt>AL_AliasSet</tt>) for this register alias
+set.