Update tblgen command guide. Remove unused tblgen InstrEnumEmitter files.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151513 91177308-0d34-0410-b5e6-96231b3b80d8

1 files changed, 38 insertions, 14 deletions

diff --git a/docs/CommandGuide/tblgen.pod b/docs/CommandGuide/tblgen.pod
index fe1be5ecfa..180bcc1769 100644
--- a/docs/CommandGuide/tblgen.pod
+++ b/docs/CommandGuide/tblgen.pod
@@ -41,6 +41,10 @@ Specify where to find other target description files for inclusion. The
 F<directory> value should be a full or partial path to a directory that contains
 target description files.
 
+=item B<-asmparsernum> F<N>
+
+Make -gen-asm-parser emit assembly writer number F<N>.
+
 =item B<-asmwriternum> F<N>
 
 Make -gen-asm-writer emit assembly writer number F<N>.
@@ -57,38 +61,50 @@ Print all records to standard output (default).
 
 Print enumeration values for a class
 
-=item B<-gen-emitter>
+=item B<-print-sets>
 
-Generate machine code emitter.
+Print expanded sets for testing DAG exprs.
 
-=item B<-gen-register-enums>
+=item B<-gen-emitter>
 
-Generate the enumeration values for all registers.
+Generate machine code emitter.
 
-=item B<-gen-register-desc>
+=item B<-gen-register-info>
 
-Generate a register info description for each register.
+Generate registers and register classes info.
 
-=item B<-gen-register-desc-header>
+=item B<-gen-instr-info>
 
-Generate a register info description header for each register.
+Generate instruction descriptions.
 
-=item B<-gen-instr-enums>
+=item B<-gen-asm-writer>
 
-Generate enumeration values for instructions.
+Generate the assembly writer.
 
-=item B<-gen-instr-desc>
+=item B<-gen-disassembler>
 
-Generate instruction descriptions.
+Generate disassembler.
 
-=item B<-gen-asm-writer>
+=item B<-gen-pseudo-lowering>
 
-Generate the assembly writer.
+Generate pseudo instruction lowering.
 
 =item B<-gen-dag-isel>
 
 Generate a DAG (Directed Acycle Graph) instruction selector.
 
+=item B<-gen-asm-matcher>
+
+Generate assembly instruction matcher.
+
+=item B<-gen-dfa-packetizer>
+
+Generate DFA Packetizer for VLIW targets.
+
+=item B<-gen-fast-isel>
+
+Generate a "fast" instruction selector.
+
 =item B<-gen-subtarget>
 
 Generate subtarget enumerations.
@@ -97,6 +113,14 @@ Generate subtarget enumerations.
 
 Generate intrinsic information.
 
+=item B<-gen-tgt-intrinsic>
+
+Generate target intrinsic information.
+
+=item B<-gen-enhanced-disassembly-info>
+
+Generate enhanced disassembly info.
+
 =item B<-version>
 
 Show the version number of this program.