diff options
| author | Eric Christopher <echristo@apple.com> | 2010-08-20 00:36:24 +0000 |
|---|---|---|
| committer | Eric Christopher <echristo@apple.com> | 2010-08-20 00:36:24 +0000 |
| commit | f762fbe4fa421c91e20044ee009ddb57e25dd135 (patch) | |
| tree | b94352d33ff02419f4f6569cfc8d97ac1e961c3f | |
| parent | cb59229a4a60abaee9ef060c515dbd3513865afd (diff) | |
Fix loop conditionals (MO.isDef() asserts that it's a reg) and
move some constraints around.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111594 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/ARM/ARMFastISel.cpp | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/lib/Target/ARM/ARMFastISel.cpp b/lib/Target/ARM/ARMFastISel.cpp index a61fca1f25..6281c3a3b0 100644 --- a/lib/Target/ARM/ARMFastISel.cpp +++ b/lib/Target/ARM/ARMFastISel.cpp @@ -122,7 +122,8 @@ bool ARMFastISel::DefinesOptionalPredicate(MachineInstr *MI, bool *CPSR) { // Look to see if our OptionalDef is defining CPSR or CCR. for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { const MachineOperand &MO = MI->getOperand(i); - if (MO.isDef() && MO.isReg() && MO.getReg() == ARM::CPSR) + if (!MO.isReg() || !MO.isDef()) continue; + if (MO.getReg() == ARM::CPSR) *CPSR = true; } return true; |