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authorEvan Cheng <evan.cheng@apple.com>2007-02-17 11:04:35 +0000
committerEvan Cheng <evan.cheng@apple.com>2007-02-17 11:04:35 +0000
commitefdcb839f20d09fd1e0455194b9a1df87d2d3a59 (patch)
treec8bda0e812242e79cca1ef03a1904ba310b2f301
parentdee5a5a52c45d04aa9f64a7b6e2adae37878a304 (diff)
- Added regsOverlap() to test if two registers overlap. Or in case they are
virtual registers, test if they the same. - Added a virtual method to return target specific reserved registers, e.g. SP. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34375 91177308-0d34-0410-b5e6-96231b3b80d8
-rw-r--r--include/llvm/Target/MRegisterInfo.h17
1 files changed, 17 insertions, 0 deletions
diff --git a/include/llvm/Target/MRegisterInfo.h b/include/llvm/Target/MRegisterInfo.h
index 6d53d51456..da111e6ce6 100644
--- a/include/llvm/Target/MRegisterInfo.h
+++ b/include/llvm/Target/MRegisterInfo.h
@@ -284,6 +284,17 @@ public:
return false;
}
+ /// regsOverlap - Returns true if the two registers are equal or alias
+ /// each other. The registers may be virtual register.
+ bool regsOverlap(unsigned regA, unsigned regB) const {
+ if (regA == regB)
+ return true;
+
+ if (isVirtualRegister(regA) || isVirtualRegister(regB))
+ return false;
+ return areAliases(regA, regB);
+ }
+
/// getCalleeSavedRegs - Return a null-terminated list of all of the
/// callee saved registers on this target. The register should be in the
/// order of desired callee-save stack frame offset. The first register is
@@ -295,6 +306,12 @@ public:
/// length of this list match the getCalleeSaveRegs() list.
virtual const TargetRegisterClass* const *getCalleeSavedRegClasses() const =0;
+ /// getReservedRegs - Returns a bitset indexed by physical register number
+ /// indicating if a register is a special register that has particular uses and
+ /// should be considered unavailable at all times, e.g. SP, RA. This is used by
+ /// register scavenger to determine what registers are free.
+ virtual BitVector getReservedRegs(const MachineFunction &MF) const = 0;
+
//===--------------------------------------------------------------------===//
// Register Class Information
//