Push ops list, asm string, and pattern all the way up to InstV8. Move the

InstV8 class to the InstrFormats file where it belongs.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24824 91177308-0d34-0410-b5e6-96231b3b80d8

4 files changed, 56 insertions, 96 deletions

diff --git a/lib/Target/Sparc/SparcInstrFormats.td b/lib/Target/Sparc/SparcInstrFormats.td
index 1e73121372..9b15aeed50 100644
--- a/lib/Target/Sparc/SparcInstrFormats.td
+++ b/lib/Target/Sparc/SparcInstrFormats.td
@@ -7,11 +7,26 @@
 // 
 //===----------------------------------------------------------------------===//
 
+class InstV8<dag ops, string asmstr, list<dag> pattern> : Instruction {
+  field bits<32> Inst;
+
+  let Namespace = "V8";
+
+  bits<2> op;
+  let Inst{31-30} = op;               // Top two bits are the 'op' field
+  
+  dag OperandList = ops;
+  let AsmString   = asmstr;
+  let Pattern = pattern;
+}
+
 //===----------------------------------------------------------------------===//
 // Format #2 instruction classes in the SparcV8
 //===----------------------------------------------------------------------===//
 
-class F2 : InstV8 {                   // Format 2 instructions
+// Format 2 instructions
+class F2<dag ops, string asmstr, list<dag> pattern>
+   : InstV8<ops, asmstr, pattern> {
   bits<3>  op2;
   bits<22> imm22;
   let op          = 0;    // op = 0
@@ -21,27 +36,20 @@ class F2 : InstV8 {                   // Format 2 instructions
 
 // Specific F2 classes: SparcV8 manual, page 44
 //
-class F2_1<bits<3> op2Val, dag ops, string asmstr, list<dag> pattern> : F2 {
+class F2_1<bits<3> op2Val, dag ops, string asmstr, list<dag> pattern>
+   : F2<ops, asmstr, pattern> {
   bits<5>  rd;
 
-  dag OperandList = ops;
-  let AsmString   = asmstr;
-  let Pattern = pattern;
-
   let op2         = op2Val;
 
   let Inst{29-25} = rd;
 }
 
 class F2_2<bits<4> condVal, bits<3> op2Val, dag ops, string asmstr, 
-           list<dag> pattern> : F2 {
+           list<dag> pattern> : F2<ops, asmstr, pattern> {
   bits<4>   cond;
   bit       annul = 0;     // currently unused
 
-  dag OperandList = ops;
-  let AsmString   = asmstr;
-  let Pattern = pattern;
-
   let cond        = condVal;
   let op2         = op2Val;
 
@@ -53,7 +61,8 @@ class F2_2<bits<4> condVal, bits<3> op2Val, dag ops, string asmstr,
 // Format #3 instruction classes in the SparcV8
 //===----------------------------------------------------------------------===//
 
-class F3 : InstV8 {
+class F3<dag ops, string asmstr, list<dag> pattern>
+    : InstV8<ops, asmstr, pattern> {
   bits<5> rd;
   bits<6> op3;
   bits<5> rs1;
@@ -66,14 +75,10 @@ class F3 : InstV8 {
 // Specific F3 classes: SparcV8 manual, page 44
 //
 class F3_1<bits<2> opVal, bits<6> op3val, dag ops,
-           string asmstr, list<dag> pattern> : F3 {
+           string asmstr, list<dag> pattern> : F3<ops, asmstr, pattern> {
   bits<8> asi = 0; // asi not currently used in SparcV8
   bits<5> rs2;
 
-  dag OperandList = ops;
-  let AsmString   = asmstr;
-  let Pattern = pattern;
-
   let op         = opVal;
   let op3        = op3val;
 
@@ -83,13 +88,9 @@ class F3_1<bits<2> opVal, bits<6> op3val, dag ops,
 }
 
 class F3_2<bits<2> opVal, bits<6> op3val, dag ops, 
-           string asmstr, list<dag> pattern> : F3 {
+           string asmstr, list<dag> pattern> : F3<ops, asmstr, pattern> {
   bits<13> simm13;
 
-  dag OperandList = ops;
-  let AsmString   = asmstr;
-  let Pattern = pattern;
-
   let op         = opVal;
   let op3        = op3val;
 
@@ -99,13 +100,9 @@ class F3_2<bits<2> opVal, bits<6> op3val, dag ops,
 
 // floating-point
 class F3_3<bits<2> opVal, bits<6> op3val, bits<9> opfval, dag ops,
-           string asmstr, list<dag> pattern> : F3 {
+           string asmstr, list<dag> pattern> : F3<ops, asmstr, pattern> {
   bits<5> rs2;
 
-  dag OperandList = ops;
-  let AsmString   = asmstr;
-  let Pattern = pattern;
-
   let op         = opVal;
   let op3        = op3val;
 
diff --git a/lib/Target/Sparc/SparcInstrInfo.td b/lib/Target/Sparc/SparcInstrInfo.td
index 545b8923ed..46d1d3a9ae 100644
--- a/lib/Target/Sparc/SparcInstrInfo.td
+++ b/lib/Target/Sparc/SparcInstrInfo.td
@@ -15,19 +15,6 @@
 // Instruction format superclass
 //===----------------------------------------------------------------------===//
 
-class InstV8 : Instruction {          // SparcV8 instruction baseline
-  field bits<32> Inst;
-
-  let Namespace = "V8";
-
-  bits<2> op;
-  let Inst{31-30} = op;               // Top two bits are the 'op' field
-
-  // Bit attributes specific to SparcV8 instructions
-  bit isPasi       = 0; // Does this instruction affect an alternate addr space?
-  bit isPrivileged = 0; // Is this a privileged instruction?
-}
-
 include "SparcV8InstrFormats.td"
 
 //===----------------------------------------------------------------------===//
@@ -101,11 +88,9 @@ def V8selectfcc : SDNode<"V8ISD::SELECT_FCC", SDTV8selectcc>;
 //===----------------------------------------------------------------------===//
 
 // Pseudo instructions.
-class Pseudo<dag ops, string asmstr, list<dag> pattern> : InstV8  {
-  let AsmString = asmstr;
-  dag OperandList = ops;
-  let Pattern = pattern;
-}
+class Pseudo<dag ops, string asmstr, list<dag> pattern>
+   : InstV8<ops, asmstr, pattern>;
+
 def PHI : Pseudo<(ops variable_ops), "PHI", []>;
 def ADJCALLSTACKDOWN : Pseudo<(ops i32imm:$amt), "!ADJCALLSTACKDOWN $amt",[]>;
 def ADJCALLSTACKUP : Pseudo<(ops i32imm:$amt), "!ADJCALLSTACKUP $amt", []>;
@@ -542,12 +527,10 @@ let Uses = [O0, O1, O2, O3, O4, O5], hasDelaySlot = 1, isCall = 1 in {
   // pc-relative call:
   let Defs = [O0, O1, O2, O3, O4, O5, O7, G1, G2, G3, G4, G5, G6, G7,
     D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15] in
-  def CALL : InstV8 {
-    let OperandList = (ops IntRegs:$dst);
+  def CALL : InstV8<(ops IntRegs:$dst), "call $dst", []> {
     bits<30> disp;
     let op = 1;
     let Inst{29-0} = disp;
-    let AsmString = "call $dst";
   }
 
   // indirect call (O7 is an EXPLICIT def in indirect calls, so it cannot also
diff --git a/lib/Target/SparcV8/SparcV8InstrFormats.td b/lib/Target/SparcV8/SparcV8InstrFormats.td
index 1e73121372..9b15aeed50 100644
--- a/lib/Target/SparcV8/SparcV8InstrFormats.td
+++ b/lib/Target/SparcV8/SparcV8InstrFormats.td
@@ -7,11 +7,26 @@
 // 
 //===----------------------------------------------------------------------===//
 
+class InstV8<dag ops, string asmstr, list<dag> pattern> : Instruction {
+  field bits<32> Inst;
+
+  let Namespace = "V8";
+
+  bits<2> op;
+  let Inst{31-30} = op;               // Top two bits are the 'op' field
+  
+  dag OperandList = ops;
+  let AsmString   = asmstr;
+  let Pattern = pattern;
+}
+
 //===----------------------------------------------------------------------===//
 // Format #2 instruction classes in the SparcV8
 //===----------------------------------------------------------------------===//
 
-class F2 : InstV8 {                   // Format 2 instructions
+// Format 2 instructions
+class F2<dag ops, string asmstr, list<dag> pattern>
+   : InstV8<ops, asmstr, pattern> {
   bits<3>  op2;
   bits<22> imm22;
   let op          = 0;    // op = 0
@@ -21,27 +36,20 @@ class F2 : InstV8 {                   // Format 2 instructions
 
 // Specific F2 classes: SparcV8 manual, page 44
 //
-class F2_1<bits<3> op2Val, dag ops, string asmstr, list<dag> pattern> : F2 {
+class F2_1<bits<3> op2Val, dag ops, string asmstr, list<dag> pattern>
+   : F2<ops, asmstr, pattern> {
   bits<5>  rd;
 
-  dag OperandList = ops;
-  let AsmString   = asmstr;
-  let Pattern = pattern;
-
   let op2         = op2Val;
 
   let Inst{29-25} = rd;
 }
 
 class F2_2<bits<4> condVal, bits<3> op2Val, dag ops, string asmstr, 
-           list<dag> pattern> : F2 {
+           list<dag> pattern> : F2<ops, asmstr, pattern> {
   bits<4>   cond;
   bit       annul = 0;     // currently unused
 
-  dag OperandList = ops;
-  let AsmString   = asmstr;
-  let Pattern = pattern;
-
   let cond        = condVal;
   let op2         = op2Val;
 
@@ -53,7 +61,8 @@ class F2_2<bits<4> condVal, bits<3> op2Val, dag ops, string asmstr,
 // Format #3 instruction classes in the SparcV8
 //===----------------------------------------------------------------------===//
 
-class F3 : InstV8 {
+class F3<dag ops, string asmstr, list<dag> pattern>
+    : InstV8<ops, asmstr, pattern> {
   bits<5> rd;
   bits<6> op3;
   bits<5> rs1;
@@ -66,14 +75,10 @@ class F3 : InstV8 {
 // Specific F3 classes: SparcV8 manual, page 44
 //
 class F3_1<bits<2> opVal, bits<6> op3val, dag ops,
-           string asmstr, list<dag> pattern> : F3 {
+           string asmstr, list<dag> pattern> : F3<ops, asmstr, pattern> {
   bits<8> asi = 0; // asi not currently used in SparcV8
   bits<5> rs2;
 
-  dag OperandList = ops;
-  let AsmString   = asmstr;
-  let Pattern = pattern;
-
   let op         = opVal;
   let op3        = op3val;
 
@@ -83,13 +88,9 @@ class F3_1<bits<2> opVal, bits<6> op3val, dag ops,
 }
 
 class F3_2<bits<2> opVal, bits<6> op3val, dag ops, 
-           string asmstr, list<dag> pattern> : F3 {
+           string asmstr, list<dag> pattern> : F3<ops, asmstr, pattern> {
   bits<13> simm13;
 
-  dag OperandList = ops;
-  let AsmString   = asmstr;
-  let Pattern = pattern;
-
   let op         = opVal;
   let op3        = op3val;
 
@@ -99,13 +100,9 @@ class F3_2<bits<2> opVal, bits<6> op3val, dag ops,
 
 // floating-point
 class F3_3<bits<2> opVal, bits<6> op3val, bits<9> opfval, dag ops,
-           string asmstr, list<dag> pattern> : F3 {
+           string asmstr, list<dag> pattern> : F3<ops, asmstr, pattern> {
   bits<5> rs2;
 
-  dag OperandList = ops;
-  let AsmString   = asmstr;
-  let Pattern = pattern;
-
   let op         = opVal;
   let op3        = op3val;
 
diff --git a/lib/Target/SparcV8/SparcV8InstrInfo.td b/lib/Target/SparcV8/SparcV8InstrInfo.td
index 545b8923ed..46d1d3a9ae 100644
--- a/lib/Target/SparcV8/SparcV8InstrInfo.td
+++ b/lib/Target/SparcV8/SparcV8InstrInfo.td
@@ -15,19 +15,6 @@
 // Instruction format superclass
 //===----------------------------------------------------------------------===//
 
-class InstV8 : Instruction {          // SparcV8 instruction baseline
-  field bits<32> Inst;
-
-  let Namespace = "V8";
-
-  bits<2> op;
-  let Inst{31-30} = op;               // Top two bits are the 'op' field
-
-  // Bit attributes specific to SparcV8 instructions
-  bit isPasi       = 0; // Does this instruction affect an alternate addr space?
-  bit isPrivileged = 0; // Is this a privileged instruction?
-}
-
 include "SparcV8InstrFormats.td"
 
 //===----------------------------------------------------------------------===//
@@ -101,11 +88,9 @@ def V8selectfcc : SDNode<"V8ISD::SELECT_FCC", SDTV8selectcc>;
 //===----------------------------------------------------------------------===//
 
 // Pseudo instructions.
-class Pseudo<dag ops, string asmstr, list<dag> pattern> : InstV8  {
-  let AsmString = asmstr;
-  dag OperandList = ops;
-  let Pattern = pattern;
-}
+class Pseudo<dag ops, string asmstr, list<dag> pattern>
+   : InstV8<ops, asmstr, pattern>;
+
 def PHI : Pseudo<(ops variable_ops), "PHI", []>;
 def ADJCALLSTACKDOWN : Pseudo<(ops i32imm:$amt), "!ADJCALLSTACKDOWN $amt",[]>;
 def ADJCALLSTACKUP : Pseudo<(ops i32imm:$amt), "!ADJCALLSTACKUP $amt", []>;
@@ -542,12 +527,10 @@ let Uses = [O0, O1, O2, O3, O4, O5], hasDelaySlot = 1, isCall = 1 in {
   // pc-relative call:
   let Defs = [O0, O1, O2, O3, O4, O5, O7, G1, G2, G3, G4, G5, G6, G7,
     D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15] in
-  def CALL : InstV8 {
-    let OperandList = (ops IntRegs:$dst);
+  def CALL : InstV8<(ops IntRegs:$dst), "call $dst", []> {
     bits<30> disp;
     let op = 1;
     let Inst{29-0} = disp;
-    let AsmString = "call $dst";
   }
 
   // indirect call (O7 is an EXPLICIT def in indirect calls, so it cannot also