diff options
| author | Duncan Sands <baldrick@free.fr> | 2010-10-21 16:06:28 +0000 |
|---|---|---|
| committer | Duncan Sands <baldrick@free.fr> | 2010-10-21 16:06:28 +0000 |
| commit | dbbd99faf1d661f03a9dfc1551d7537c34d64bee (patch) | |
| tree | 908b1159fdd0e34898928345b72f3def54f71b90 | |
| parent | 2b55f56df8a69dd2fc057626e314cdf29d7c10ed (diff) | |
The return value of this call is not used, so no point
in assigning it to a variable (gcc-4.6 warning).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117024 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/ARM/ARMExpandPseudoInsts.cpp | 15 |
1 files changed, 7 insertions, 8 deletions
diff --git a/lib/Target/ARM/ARMExpandPseudoInsts.cpp b/lib/Target/ARM/ARMExpandPseudoInsts.cpp index 0275a505e8..389fd19a8e 100644 --- a/lib/Target/ARM/ARMExpandPseudoInsts.cpp +++ b/lib/Target/ARM/ARMExpandPseudoInsts.cpp @@ -628,14 +628,13 @@ bool ARMExpandPseudo::ExpandMBB(MachineBasicBlock &MBB) { case ARM::MOVsrl_flag: case ARM::MOVsra_flag: { // These are just fancy MOVs insructions. - MachineInstrBuilder MIB = - AddDefaultPred(BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVs), - MI.getOperand(0).getReg()) - .addOperand(MI.getOperand(1)) - .addReg(0) - .addImm(ARM_AM::getSORegOpc((Opcode == ARM::MOVsrl_flag ? ARM_AM::lsr - : ARM_AM::asr), 1))) - .addReg(ARM::CPSR, RegState::Define); + AddDefaultPred(BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVs), + MI.getOperand(0).getReg()) + .addOperand(MI.getOperand(1)) + .addReg(0) + .addImm(ARM_AM::getSORegOpc((Opcode == ARM::MOVsrl_flag ? ARM_AM::lsr + : ARM_AM::asr), 1))) + .addReg(ARM::CPSR, RegState::Define); MI.eraseFromParent(); break; } |