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authorEvan Cheng <evan.cheng@apple.com>2009-03-31 19:38:51 +0000
committerEvan Cheng <evan.cheng@apple.com>2009-03-31 19:38:51 +0000
commitd54f2d571dd7faaa379eb7833536494aa4ab4609 (patch)
treea29b9c0d010f41c0ea36df4eb2aa815db63b6e43
parent968dc7a2077d5c4a0b2fca9810b0fdf9cd62991b (diff)
i128 shift libcalls are not available on x86.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68133 91177308-0d34-0410-b5e6-96231b3b80d8
-rw-r--r--lib/Target/X86/X86ISelLowering.cpp7
1 files changed, 7 insertions, 0 deletions
diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp
index f0a9484b4b..5fd981f07d 100644
--- a/lib/Target/X86/X86ISelLowering.cpp
+++ b/lib/Target/X86/X86ISelLowering.cpp
@@ -816,6 +816,13 @@ X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
setOperationAction(ISD::UMULO, MVT::i32, Custom);
setOperationAction(ISD::UMULO, MVT::i64, Custom);
+ if (!Subtarget->is64Bit()) {
+ // These libcalls are not available in 32-bit.
+ setLibcallName(RTLIB::SHL_I128, 0);
+ setLibcallName(RTLIB::SRL_I128, 0);
+ setLibcallName(RTLIB::SRA_I128, 0);
+ }
+
// We have target-specific dag combine patterns for the following nodes:
setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
setTargetDAGCombine(ISD::BUILD_VECTOR);