diff options
| author | Jim Grosbach <grosbach@apple.com> | 2010-11-11 01:27:41 +0000 |
|---|---|---|
| committer | Jim Grosbach <grosbach@apple.com> | 2010-11-11 01:27:41 +0000 |
| commit | d507d1f616be89b2327ebcd420a42075e59695b0 (patch) | |
| tree | 6d52a5961b86a26ca6908afca763e1bfb9ac93e7 | |
| parent | 336b8b42445920a3f59e42c61f2ccd9fbdfc497e (diff) | |
Fix encoding of Ra register for ARM smla* instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118761 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/ARM/ARMInstrInfo.td | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/lib/Target/ARM/ARMInstrInfo.td b/lib/Target/ARM/ARMInstrInfo.td index b5b9354187..abc1fbb89a 100644 --- a/lib/Target/ARM/ARMInstrInfo.td +++ b/lib/Target/ARM/ARMInstrInfo.td @@ -2533,7 +2533,7 @@ multiclass AI_smul<string opc, PatFrag opnode> { multiclass AI_smla<string opc, PatFrag opnode> { - def BB : AMulxyI<0b0001000, 0b00, (outs GPR:$Rd), + def BB : AMulxyIa<0b0001000, 0b00, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra), IIC_iMAC16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm, $Ra", [(set GPR:$Rd, (add GPR:$Ra, @@ -2541,35 +2541,35 @@ multiclass AI_smla<string opc, PatFrag opnode> { (sext_inreg GPR:$Rm, i16))))]>, Requires<[IsARM, HasV5TE]>; - def BT : AMulxyI<0b0001000, 0b10, (outs GPR:$Rd), + def BT : AMulxyIa<0b0001000, 0b10, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra), IIC_iMAC16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm, $Ra", [(set GPR:$Rd, (add GPR:$Ra, (opnode (sext_inreg GPR:$Rn, i16), (sra GPR:$Rm, (i32 16)))))]>, Requires<[IsARM, HasV5TE]>; - def TB : AMulxyI<0b0001000, 0b01, (outs GPR:$Rd), + def TB : AMulxyIa<0b0001000, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra), IIC_iMAC16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm, $Ra", [(set GPR:$Rd, (add GPR:$Ra, (opnode (sra GPR:$Rn, (i32 16)), (sext_inreg GPR:$Rm, i16))))]>, Requires<[IsARM, HasV5TE]>; - def TT : AMulxyI<0b0001000, 0b11, (outs GPR:$Rd), + def TT : AMulxyIa<0b0001000, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra), IIC_iMAC16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm, $Ra", [(set GPR:$Rd, (add GPR:$Ra, (opnode (sra GPR:$Rn, (i32 16)), (sra GPR:$Rm, (i32 16)))))]>, Requires<[IsARM, HasV5TE]>; - def WB : AMulxyI<0b0001001, 0b00, (outs GPR:$Rd), + def WB : AMulxyIa<0b0001001, 0b00, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra), IIC_iMAC16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm, $Ra", [(set GPR:$Rd, (add GPR:$Ra, (sra (opnode GPR:$Rn, (sext_inreg GPR:$Rm, i16)), (i32 16))))]>, Requires<[IsARM, HasV5TE]>; - def WT : AMulxyI<0b0001001, 0b10, (outs GPR:$Rd), + def WT : AMulxyIa<0b0001001, 0b10, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra), IIC_iMAC16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm, $Ra", [(set GPR:$Rd, (add GPR:$Ra, (sra (opnode GPR:$Rn, |