diff options
| author | Johnny Chen <johnny.chen@apple.com> | 2011-03-25 18:29:49 +0000 |
|---|---|---|
| committer | Johnny Chen <johnny.chen@apple.com> | 2011-03-25 18:29:49 +0000 |
| commit | ceceabd4b1e90bbddfa49799f1b3a4595dd6d99c (patch) | |
| tree | e4c8c4e19b99c00834303f159d9466a86567b480 | |
| parent | 8b2b43c41d2f9a25d1eb387bd74dd761fe3cb83b (diff) | |
Modify DisassembleThumb2LdStEx() to be more robust/correct in light of recent change to
t2LDREX/t2STREX instructions. Add two test cases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128293 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h | 12 | ||||
| -rw-r--r-- | test/MC/Disassembler/ARM/thumb-tests.txt | 6 |
2 files changed, 12 insertions, 6 deletions
diff --git a/lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h b/lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h index c2dd6a1e9e..797968840b 100644 --- a/lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h +++ b/lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h @@ -1194,8 +1194,8 @@ static bool DisassembleThumb2LdStEx(MCInst &MI, unsigned Opcode, uint32_t insn, OpIdx = 0; assert(NumOps >= 2 - && OpInfo[0].RegClass == ARM::GPRRegClassID - && OpInfo[1].RegClass == ARM::GPRRegClassID + && OpInfo[0].RegClass > 0 + && OpInfo[1].RegClass > 0 && "Expect >=2 operands and first two as reg operands"); bool isStore = (ARM::t2STREX <= Opcode && Opcode <= ARM::t2STREXH); @@ -1205,25 +1205,25 @@ static bool DisassembleThumb2LdStEx(MCInst &MI, unsigned Opcode, uint32_t insn, // Add the destination operand for store. if (isStore) { MI.addOperand(MCOperand::CreateReg( - getRegisterEnum(B, ARM::GPRRegClassID, + getRegisterEnum(B, OpInfo[OpIdx].RegClass, isSW ? decodeRs(insn) : decodeRm(insn)))); ++OpIdx; } // Source operand for store and destination operand for load. - MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID, + MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, OpInfo[OpIdx].RegClass, decodeRd(insn)))); ++OpIdx; // Thumb2 doubleword complication: with an extra source/destination operand. if (isDW) { - MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID, + MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B,OpInfo[OpIdx].RegClass, decodeRs(insn)))); ++OpIdx; } // Finally add the pointer operand. - MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID, + MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, OpInfo[OpIdx].RegClass, decodeRn(insn)))); ++OpIdx; diff --git a/test/MC/Disassembler/ARM/thumb-tests.txt b/test/MC/Disassembler/ARM/thumb-tests.txt index 666e9f5f47..ce16f750cb 100644 --- a/test/MC/Disassembler/ARM/thumb-tests.txt +++ b/test/MC/Disassembler/ARM/thumb-tests.txt @@ -154,3 +154,9 @@ # CHECK: ldrd r3, r8, [r11, #-60] 0x5b 0xe9 0x0f 0x38 + +# CHECK: ldrex r8, [r2] +0x52 0xe8 0x00 0x8f + +# CHECK: strexd r1, r7, r8, [r2] +0xc2 0xe8 0x71 0x78 |