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| author | Zhou Sheng <zhousheng00@gmail.com> | 2008-06-06 08:32:05 +0000 |
|---|---|---|
| committer | Zhou Sheng <zhousheng00@gmail.com> | 2008-06-06 08:32:05 +0000 |
| commit | cc41940dff771c98321d601e04e60dc8c67b6e87 (patch) | |
| tree | 04fa4a15c399e0d7749ebe0aa26308231be17c0a | |
| parent | 9c3c2213647e3f1b71722d61875ebac01b65cb91 (diff) | |
As Chris suggested, handle the situation if ShAmt larger than BitWidth,
otherwise, opt might crash.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52041 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Transforms/Scalar/InstructionCombining.cpp | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/lib/Transforms/Scalar/InstructionCombining.cpp b/lib/Transforms/Scalar/InstructionCombining.cpp index 05e12692f4..67c40fe21c 100644 --- a/lib/Transforms/Scalar/InstructionCombining.cpp +++ b/lib/Transforms/Scalar/InstructionCombining.cpp @@ -1236,7 +1236,7 @@ bool InstCombiner::SimplifyDemandedBits(Value *V, APInt DemandedMask, // If the input sign bit is known to be zero, or if none of the top bits // are demanded, turn this into an unsigned shift right. - if (BitWidth == ShiftAmt || RHSKnownZero[BitWidth-ShiftAmt-1] || + if (BitWidth <= ShiftAmt || RHSKnownZero[BitWidth-ShiftAmt-1] || (HighBits & ~DemandedMask) == HighBits) { // Perform the logical shift right. Value *NewVal = BinaryOperator::CreateLShr( |