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| author | Misha Brukman <brukman+llvm@gmail.com> | 2004-09-26 21:07:43 +0000 |
|---|---|---|
| committer | Misha Brukman <brukman+llvm@gmail.com> | 2004-09-26 21:07:43 +0000 |
| commit | c6e743049983dca1c6904610fa3cb78bda39d67c (patch) | |
| tree | d688bbec59685158cbdfc5e0e7de3ebad44baf8b | |
| parent | aefd04b6d0a5a3ad0011b8dffe9e5c9b88247bf7 (diff) | |
Fix the copy-pasto that Brian noticed: V8 int regs are 32-bits wide, not 64.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16518 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/Sparc/SparcRegisterInfo.td | 2 | ||||
| -rw-r--r-- | lib/Target/SparcV8/SparcV8RegisterInfo.td | 2 |
2 files changed, 2 insertions, 2 deletions
diff --git a/lib/Target/Sparc/SparcRegisterInfo.td b/lib/Target/Sparc/SparcRegisterInfo.td index 6a4da69bd6..728c115f86 100644 --- a/lib/Target/Sparc/SparcRegisterInfo.td +++ b/lib/Target/Sparc/SparcRegisterInfo.td @@ -23,7 +23,7 @@ include "../SparcRegisterInfo.td" // FIXME: the register order should be defined in terms of the preferred // allocation order... // -def IntRegs : RegisterClass<i64, 64, [L0, L1, L2, L3, L4, L5, L6, L7, +def IntRegs : RegisterClass<i32, 64, [L0, L1, L2, L3, L4, L5, L6, L7, I0, I1, I2, I3, I4, I5, G1, G2, G3, G4, G5, G6, G7, O0, O1, O2, O3, O4, O5, O7, diff --git a/lib/Target/SparcV8/SparcV8RegisterInfo.td b/lib/Target/SparcV8/SparcV8RegisterInfo.td index 6a4da69bd6..728c115f86 100644 --- a/lib/Target/SparcV8/SparcV8RegisterInfo.td +++ b/lib/Target/SparcV8/SparcV8RegisterInfo.td @@ -23,7 +23,7 @@ include "../SparcRegisterInfo.td" // FIXME: the register order should be defined in terms of the preferred // allocation order... // -def IntRegs : RegisterClass<i64, 64, [L0, L1, L2, L3, L4, L5, L6, L7, +def IntRegs : RegisterClass<i32, 64, [L0, L1, L2, L3, L4, L5, L6, L7, I0, I1, I2, I3, I4, I5, G1, G2, G3, G4, G5, G6, G7, O0, O1, O2, O3, O4, O5, O7, |